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Integrating a Microchip Gigabit Ethernet PHY into the Xilinx FPGA Ecosystem - Hardware

jafoste4

Have you ever wanted to integrate a Microchip PHY into the Xilinx Ecosystem, but previously had no proven reference designs available to mitigate risk factors? Recently Avnet released the Network FMC (http://avnet.me/fmc-network1 ), which is a dual Microchip Ethernet 10/100/1000 PHY Low Pin Count (LPC) FMC expansion module. I will take you through the design choices made in the development of the Network FMC expansion module and various lessons learned during this development process.

 

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First off let’s talk about the form factor. For this project we decided to integrate everything on a Low Pin Count (LPC) FMC form factor. We chose the FMC form factor to take advantage of the versatility of an FMC Expansion module. An FMC module can plug into any board that is FMC VITA 57 compliant. This allows for the expansion module to work with various Avnet boards such as the UltraZed product line and Xilinx development boards such as the ZC702. See https://www.vita.com/fmc for more information about FMC.

 

Next we had to determine which PHY we wanted to use for our design. In our specs we defined the PHY using three separate variables:

  • Able to operate at 10/100/1000 Mbps.
  • Support flexible I/O voltages at 3.3V/2.5V/1.8V levels to account for various development platforms that are FMC VITA 57 compliant.
  • Operates with Xilinx’s Time Sensitive Network (TSN) IP. Since it needs to be able to operate with the Xilinx TSN IP, we did not require TSN capabilities built into the PHY.

Taking these three factors into consideration, the Microchip KSZ9031RNX PHY was selected. To make this decision, we referenced both datasheets and errata documentation to verify we were meeting our requirements.

 

After the PHY was selected, we next had to look at the system level design. Specifically, what additional components/interfaces were required to integrate the KSZ9031RNX Microchip PHY to a Xilinx platform via the FMC VITA 57 specification? After reviewing, we narrowed it down to the following eight items.

 

  • MAC ID EEPROMs We implemented two MAC ID EEPROMs to allow each Microchip PHY to have their own unique network identifier To do this we used Microchip  24AA025E48-I/SN24AA025E48-I/SN which comes pre-programmed with unique MAC identifiers

 

  • 1.2V Power Supply – By default the FMC connector only provides 12V, 3.3V, and I/O voltages of 3.3v, 2.5V, or1.8V. The KSZ9031RNX PHY requires a 1.2V core voltage to operate. The manufacturer recommends two separate methods for providing it:
    1. An LDO pin that drives a P channel MOSFET to supply the 1.2V core
    2. An external 1.2V power supply.

In this case we chose to provide external power by taking the 3.3V supplied by the FMC connector and feeding it into a Microchip MIC23050-4YML-TR PWM Buck Regulator. This part is capable of sourcing 600mA by itself. Looking back in the Microchip PHYs Datasheet you will notice that the typical max current draw on the 1.2V core is 221mA. In our design, we have two KSZ9031RNX PHYs, so we accounted for double this amount or 442mA typical max current draw. This in turn gives us 158mA or 26.3% of additional current draw available to account for any anomalies or spikes allowing us to power both PHYs with the same 1.2V PWM Buck Regulator.

 

  • IPMI EEPROM An EEPROM was necessary to conform to the VITA 57 specification to allow Intelligent Platform Management Interface(IPMI configuration to occur On the Network FMC the EEPROM is configured to tell the host board to configure the host I/O levels to 1.8V If 1.8V is unavailable the host board will not provide any power to the FMC to avoid possible damage to the FMC and itself In this case we used a Microchip  AT24C02D-SSHM-TAT24C02D-SSHM-T EEPROM to accomplish this task

 

  • MAC Reference Clock – For speeds of 1Gbps, a 125MHz clock is used by the MAC. It is possible to create this clock within the FPGA however, for ease of use we decided to use a Microchip DSC1123CI2-125.0000 oscillator. This part is ideal because of the 25 PPM stability and differential signals it provides. The differential signals are routed out through the LPC FMC connector to the programmable logic for use by IP inside the host device.

 

  • PHY Reference Clock – A 25 MHz reference clock is required by the PHY to operate. This clock has very strict requirements when it comes to frequency tolerance. We chose to use the Microchip DSC1121DI2-025.0000, which has a frequency tolerance of ±25PPM. This tolerance is well within the range specified in the datasheet of ±50PPM.

 

  • RJ45 connector with Integrated Magnetics – Magnetic selection for this PHY was fairly difficult. Looking into the PHYs datasheet, it gives a few suggestions. However, none of these solutions met our requirements of being both low cost and industrial temperature rated. After a lengthy search, we settled on the L829-1J1T-32 from Bel Fuse Inc. This is a $6 (as of this post) RJ45 with integrated magnetics allowing us to save component cost and board space. To qualify these integrated magnetics, we submitted them to the Microchip LAN check. A Microchip LAN check is a free-of-charge design check service. It can be found on the Microchip website's support section. This service allows you submit your schematic capture and layout for review to Microchip system level engineers. On average they say it saves about one board spin, which I will speak to a little bit later in this article, sharing my experience with it. This check included a magnetics check against the KSZ9031RNX PHY.

 

  • Comparator LED Circuit – A comparator circuit was implemented to help engineers with ease of use. This comparator circuit controls a bi-colored LED to inform the end user what I/O voltage the host board is setting the I/O voltage to on the Network FMC.

 

  • User LEDs – User LEDs were provided to assist with development. These LEDs route to the Programmable Logic of the FPGA system to be tied to what the end user deems necessary.

 

I want to take a moment to speak about the value of the Microchip LAN check. On average they state this LAN check saves up to one PCB spin; I truly believe this. Looking back on the notes I received for this design from this service, they commented on my PHY symbol, magnetic selection, strapping resistors on the PHYs, the possible need for RGMII series termination resistors, capacitor selection size on my 1.2V generation, 25MHz oscillator accuracy, hardware reset circuit, power vias in the design, and overall temperature rating for all components. In addition to all of this, they wanted to know more specifics about my application in order to provide more specific application related suggestions such as compliance related requirements. In my personal opinion, this was a worthwhile, detailed and invaluable design service check they offer free-of-charge. I highly recommend taking advantage of this service in your next PHY design.

 

Now that we have discussed what was required from a hardware system point of view in integrating the Microchip KSZ9031RNX onto the Network FMC, you’re probably wondering how the Network FMC integrates into the Xilinx Software/Linux Ecosystem. Well, be on the lookout for the next article Integrating a Microchip Gigabit Ethernet PHY into the Xilinx FPGA Ecosystem – Software where that will be discussed.