MiniZed DDR Delay Values in Vivado Block Design

29 Mar 2018

Question: How did Avnet arrive at the DDR Delay values published in the MiniZed board definition file?

That's a good question! We developed the MiniZed board definition file with Vivado 2016.4. The settings you will find in the Avnet MiniZed board definition/awareness preset.xml are:

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Calculating these requires you to know the routing length in millimeters for the DDR clocks, DQS, and DQ traces. For MiniZed, we publish this in the net length report. You need clock and strobe for each 8 bits of data. Since MiniZed uses a single, 16-bit Micron DDR3L chip, a single clock is used for both byte groups, and there are no 3rd or 4th byte groups (since we don’t have 32-bit data).

Here’s a look at how we did this in Vivado 2016.4. First, we created a Vivado project targeting the Zynq 7007S in the CLG225 package. We created a new block design with Zynq PS7 IP, and then we customized the Zynq PS7. In the customization menu, you can change the Training/Board Details from User Input to Calculated:

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Here are the relevant lines from the MiniZed trace length report.

Byte Group 0

D3L_CK_N, Signal Layers Only, 27.1095mm
D3L_CK_P, Signal Layers Only, 26.2719mm
D3L_LDQS_N, Signal Layers Only, 19.9906mm
D3L_LDQS_P, Signal Layers Only, 20.5343mm
D3L_DQ0, Signal Layers Only, 24.338mm
D3L_DQ1, Signal Layers Only, 20.3481mm
D3L_DQ2, Signal Layers Only, 19.0871mm
D3L_DQ3, Signal Layers Only, 23.6634mm
D3L_DQ4, Signal Layers Only, 17.4953mm
D3L_DQ5, Signal Layers Only, 18.4476mm
D3L_DQ6, Signal Layers Only, 19.8552mm
D3L_DQ7, Signal Layers Only, 17.694mm

Byte Group 1

D3L_CK_N, Signal Layers Only, 27.1095mm
D3L_CK_P, Signal Layers Only, 26.2719mm
D3L_UDQS_N, Signal Layers Only, 24.2622mm
D3L_UDQS_P, Signal Layers Only, 23.7328mm
D3L_DQ8, Signal Layers Only, 24.0816mm
D3L_DQ9, Signal Layers Only, 21.8845mm
D3L_DQ10, Signal Layers Only, 24.3411mm
D3L_DQ11, Signal Layers Only, 23.2585mm
D3L_DQ12, Signal Layers Only, 25.6319mm
D3L_DQ13, Signal Layers Only, 24.4435mm
D3L_DQ14, Signal Layers Only, 24.3381mm
D3L_DQ15, Signal Layers Only, 27.0672mm

Average the P and N of the differential signals. Average the maximum and minimums within the DQ byte groups. Then you get:

CLK0 = (D3L_CK_P + D3L_CK_N)/2 = (27.1095+26.271)/2 = 26.6907mm
DQS0 = (D3L_LDQS_N + D3L_LDQS_P)/2 = (19.9906+20.5343)/2 = 20.26245mm
DQ[7:0] = (DQ0 + DQ4)/2 = (24.338+17.4953)/2 = 20.91665mm

CLK1 = (D3L_CK_P + D3L_CK_N)/2 = (27.1095+26.271)/2 = 26.6907mm
DQS1 = (D3L_UDQS_N + D3L_UDQS_P)/2 = (24.2622+23.7328)/2 = 23.9975mm
DQ[15:8] = (DQ15 + DQ9)/2 = (27.0672+21.8845)/2 = 24.47585mm

However, since the 7007S CLG225 was still early release in 2016.4, Xilinx did not have the correct package delay values.

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We recognized the package delay inaccuracy. Instead of correcting the package delays in this calculation table, we created our own spreadsheet which compensated for the routing lengths and package delays. This allowed us to calculate an equivalent millimeter length for the entire path. See below what actually got entered during the original MiniZed board definition calculations for the DDR tuning parameters. Note that the entries for CLK2, CLK3, DQS2, DQS3, DQ[23:16], and DQ[31:24] are all irrelevant since they don’t exist on this board. We added in some whole numbers to make sure we didn’t encounter negative values in the calculations for DQS to CLK and DQ Board Delay for the non-existent Byte Groups 2 and 3. You will see that the values for Byte Groups 0 and 1 match the board definition:

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We recently reviewed these parameters in 2017.4. Notice that the default calculation table does have the correct package values for the 7007S CLG225.

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This allows us to use the PCB trace length values without calculating the total path delay manually. (Again, ignore all values relative to Byte Groups 2 and 3).

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This leads to the following inputs in the 2017.4 version of the board definition file (negative values replaced with 0):

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0" value="0.232"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1" value="0.231"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2" value="0.318"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3" value="0.433"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0" value="0.045"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1" value="0.046"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2" value="0.000"/>

<user_parameter name="CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3" value="0.000"/>

Comparing the relevant 2016.4 calculations (manually included package delays) vs. the 2017.4 calculations (auto-included package delays) for Byte Groups 0 and 1, we see the following differences:

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You will notice that all of these differences are very small. Furthermore, the Zynq DDR3 controller’s capability to auto-tune means that you will get the same result in a memory performance test regardless of whether you enter the 2016.4 or 2017.4 values. Not too bad for early tool support and manually including package delays!

If you’re interested in more detail, check out Appendix A in Lab 2 of Avnet’s Developing Zynq Hardware (Vivado 2017.1) Speedway where all of this is explained.

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