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  • Author Author: Jan Cumps
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online lesson: clock domain crossing with a VHDL frequency counter - part 1: simulation in Vivado

Jan Cumps
online lesson: clock domain crossing with a VHDL frequency counter - part 1: simulation in Vivado

When your design has more than a single clock, you'll have to deal with cross-clock-domain situations. In my search for good online trainings, I bumped on this example from SURF-VHDL: How to compute the frequency of a clock. In this example, you have the usual clock for your design (called Reference Clock in the example). And a clock signal that you want to know the frequency of (called Test Clock here). A small VHDL design counts the frequency of the test clock. In order to have the HDL synthesiser do a proper synthesis, that second clock domain has to be synchronised with the primary clock that drives the counting. The example shows a technique to do that. 

This exercise is also an excuse to check if the SURF-VHDL tutorials are good (Yes, they are), and check how simulation in Vivado compares to the Xilinx ISE editor for Spartan 6. I will not provide the full sources and testbed for this example. The source is available from the link I posted above. The test bed and 4 videos digging into the detail of the design, are available when you subscribe to the SURF-VHDL tutorials (no charge). The tutorial uses Quartus, a DE0 kit and an Altera Celeron device. For this first part of my review, this doesn't matter. Everything is vendor-independent.

In part 2, where this frequency counter is used in a design, there will be differences. Because I'll use different clock sources and a different display. What you see below, is the result of simulating a test frequency that's 10 times faster than the reference frequency. Each 4096 clock ticks, the test counter counts to 40960. You see that in the picture below.

image

To do the simulation in Vivado, I added the SURF-VHDL test bed to the simulation sources, then ran a simulation for 1 ms. As expected, the results are the same as in Altera ModelSim.

What will I do in part 2?

  • the test clock will be generated by a Spartan-7 mixed-mode clock manager.
  • the Arty board doesn't have a display, or something that can show a 16 bit value. I could externalise the counter and use a logic analyser, or try working with the UART block and send the count to a PC ...
Parents Comment
  • in reply to michaelkellett

    I modified the reset, so that (I think) it's synchronous:

    --  CLOCK REFERENCE domain
p_counter_ref : process (i_rstb,i_clk_ref)
begin
  if(rising_edge(i_clk_ref)) then
    if(i_rstb='0') then
      r1_counter_ref                 <= (others=>'0');
      r1_counter_test_ena            <= '0';
      r1_counter_test_strobe         <= '0';
      r1_counter_test_rstb           <= '0';
    else

    I'll check whet to do to separate the signals to-be-reset process from the ones that don't play in the reset logic ...

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