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Blog Program MiniZed over WiFi using Simulink
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  • Author Author: mbrown
  • Date Created: 15 Feb 2018 11:02 PM Date Created
  • Views 2684 views
  • Likes 6 likes
  • Comments 17 comments
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Program MiniZed over WiFi using Simulink

mbrown
mbrown
15 Feb 2018

Though MiniZed be but small, she is fierce.

 

A terrible use of Shakespeare’s famous quote, but still a perfect fit for MiniZedTm and its Xilinx ZynqTm SoC.

 

In this blog we’ll explore a new way to program this fierce little board without being an SoC expert.

 

At first glance it may be daunting to start your design, but there’s good news for anyone new to SoC programming. Avnet created a support package to enable you to program MiniZed using code generation directly from SimulinkRegistered. This means that you don’t need to be an SoC expert or write a single line of HDL or C code. Instead we leverage the MathWorks Guided Workflow for Zynq, allowing you to explore at the application level.

 

You can also impress your friends by doing it all over WiFi – no cords!

image

Start your design in Simulink. Once you’ve perfected your algorithm model and the simulations look good, the code generation tools will handle the minutia of IP peripheral creation, AXI4 data movement, Linux device drivers, application code, and finally building and executing the deployed model on MiniZed. That’s a mouthful!

 

Here’s a simplified diagram to help you visualize what’s automatically created for you. In a word – everything.  You just need to come up with the algorithm. The tools do the rest.

image

 

Not shown here, but extremely useful, is the ability to communicate with your deployed model from Simulink through a network connection. This can be either a USB-to-Ethernet adapter, or wirelessly through your WiFi router.

 

Simulink comes from MathWorks, the makers of MATLABRegistered. Both tools are familiar to engineers who need to model and simulate computational algorithms. The Avnet MiniZed Support Package for Simulink provides the customizations needed to target the hardware on MiniZed. The package can be downloaded from MATLAB’s Add-On Explorer or on the web at MATLAB File Exchange (search for ‘avnet minized’).

 

Installation is just a few mouse clicks. It includes a Getting Started tutorial to walk you through your first design – blinking an LED (of course). From there, you can start designing your own algorithm for MiniZed.

image

You won’t need to set aside an entire Tuesday to get started. Get a cup of coffee and try it out one morning this week.

 

Just another way to have some fun with this fierce little board.

 

If you don't have a MiniZed yet, click this link: Buy MiniZedBuy MiniZed

 

Enjoy!

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Top Comments

  • michaelkellett
    michaelkellett over 7 years ago in reply to genebren +4
    Before you get too carried away try checking out the cost of the other software you need to use this: https://uk.mathworks.com/matlabcentral/fileexchange/66004-avnet-minized-support-package-for-simulink…
  • weiwei2
    weiwei2 over 7 years ago in reply to mbrown +2
    ok this solves the problem. It is my mistake to have miss this step
  • genebren
    genebren over 7 years ago +1
    Nice write up. Soon you will have everyone writing code for FPGAs.
  • mbrown
    mbrown over 7 years ago in reply to weiwei2

    Best guess is that something in the IP catalog was rev'd between 2017.2 and 2017.4, which is now breaking the scripted TCL build.

    Unfortunately you're in the wilderness once you rename tool installation directory names.

    Good luck!

    /Matt

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  • weiwei2
    weiwei2 over 7 years ago in reply to mbrown

    How do i select 2016.4? i attempted a workaround, i install 2017.4 but rename the folder as 2017.2 and it manage to be setup for embedded coder support for zynq. after that i am able to run the workflow advisor up to step 4.1 and get this error. wonder if you can suggest what i can attempt

     

    ## }

    ## create_root_design ""

    create_bd_cell: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 459.129 ; gain = 128.973

    WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '10.000' to '20.000' has been ignored for IP 'clk_wiz_0'

    WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '20.000' has been ignored for IP 'clk_wiz_0'

    WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN2_PERIOD' from '10.000' to '10.0' has been ignored for IP 'clk_wiz_0'

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_O is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_T is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CLK is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CMD_O is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CMD_T is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_DATA_O is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_DATA_T is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/GPIO_I is being overridden by the user. This pin will not be connected as a part of interface connection GPIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CDN is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CLK_FB is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1731] Type mismatch between connected pins: /processing_system7_0/SDIO0_CLK_FB(clk) and /wireless_mgr_0/SDIO_CLK_FB(undef)

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_CMD_I is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_DATA_I is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    WARNING: [BD 41-1306] The connection to interface pin /processing_system7_0/SDIO0_WP is being overridden by the user. This pin will not be connected as a part of interface connection SDIO_0

    Wrote : <C:/matlabfiles/minized/hdl_prj/vivado_ip_prj/vivado_prj.srcs/sources_1/bd/design_1/design_1.bd>

    # set_property synth_checkpoint_mode None [get_files design_1.bd]

    # validate_bd_design

    ERROR: [BD 41-1811] The interconnect </axi_interconnect_0> is missing a valid master Interface connection

    ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

     

      while executing

    "validate_bd_design"

      (file "vivado_create_prj.tcl" line 17)

    INFO: [Common 17-206] Exiting Vivado at Fri Mar 23 20:38:32 2018...

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  • mbrown
    mbrown over 7 years ago in reply to weiwei2

    We have not tested with 2018a yet. However, it is possible to select 2016.4 SDK and it should work since the single-core Zynq 7007S is supported in that version.

     

    I'll post an update once we have tested with 2018a.

     

    Thanks for your interest!

    /Matt

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  • weiwei2
    weiwei2 over 7 years ago in reply to mbrown

    R2018a is just out, do you know if there is still a hard limit in it for 2017.2? (currently under embedded coder setup settings it is checking for 2017.2)

    alternatively, i heard of a way to let minized to use 2016.4 then it won't have windows 10 problem, but i prefer the first way if it is achievable

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  • weiwei2
    weiwei2 over 7 years ago in reply to weiwei2

    ok i finally got it working on my windows 7 machine and the Vivado 2017.2 has no issue over there. Completed the 4 bit counter led blinking example, with external mode working after some minor settings. thanks for the reply and help

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