I have a single seven segment display with common anode. This display has following symbol: FJS-5161B. Here is brief information from datasheet for this display:
I have created a kind of PMOD module which contains a single seven segment display, eight resistors with value 150 ohm for limit the LEDs current and pinout socket.
Here is photo of this module:
Here is information about connection between Pmod JD connector and seven segment display:
V15 jd[0] -> D
U12 jd[1] -> C
V13 jd[2] -> B
T12 jd[3] -> A
T13 jd[4] -> DP
R11 jd[5] -> G
T11 jd[6] -> F
U11 jd[7] -> E
I have used Pmod JD connector with their eight pin to direct drive of this module by Arty S7 board. I have created simple module in Verilog which allow to drive this display. Here is source code:
module display(
input CLK100MHZ,
input [3:0] digit,
output [7:0] jd
);
reg [7:0] outValue;
always @(posedge CLK100MHZ)
begin
case (digit)
4'h0: outValue <= 8'b00110000;
4'h1: outValue <= 8'b11111001;
4'h2: outValue <= 8'b01010010;
4'h3: outValue <= 8'b11010000;
4'h4: outValue <= 8'b10011001;
4'h5: outValue <= 8'b10010100;
4'h6: outValue <= 8'b00010100;
4'h7: outValue <= 8'b11110001;
4'h8: outValue <= 8'b00010000;
4'h9: outValue <= 8'b10010000;
default: outValue <= 8'b11111111;
endcase
end
assign jd = outValue;
endmoduleWe have here a simple conversion of input digit stored at 4 bits to 8 bits output register which drives output JD pins. Here is source of main design for test this module:
module top(
input CLK100MHZ,
output [7:0] jd
);
reg [3:0] digit = 0;
display display(
.CLK100MHZ(CLK100MHZ),
.digit(digit),
.jd(jd)
);
reg [32:0] countReg = 0;
always @(posedge CLK100MHZ) begin
if (countReg < 99999999) begin
countReg <= countReg + 1;
end else begin
countReg <= 0;
if (digit < 9)
digit <= digit + 1;
else
digit <= 0;
end
end
endmoduleWe have here simple prescaler of source 100 MHz clock. So, in each second we are able to see a different digit on display.
Here is short video presentation of a working display:
Below there is small the same code of display with support for dot point and basic brightness regulation with 15 levels:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22.09.2018 23:43:36
// Design Name: kk99
// Module Name: display
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.02 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module display(
input CLK100MHZ,
input [3:0] digit,
input dotPoint,
input [3:0] pulseDuration,
output [7:0] jd
);
reg [3:0] pulseStep = 0;
reg [7:0] outValue;
always @(posedge CLK100MHZ) begin
if (pulseStep < pulseDuration) begin
pulseStep <= pulseStep + 1;
if (dotPoint) begin
case (digit)
4'h0: outValue <= 8'b00100000;
4'h1: outValue <= 8'b11101001;
4'h2: outValue <= 8'b01000010;
4'h3: outValue <= 8'b11000000;
4'h4: outValue <= 8'b10001001;
4'h5: outValue <= 8'b10000100;
4'h6: outValue <= 8'b00000100;
4'h7: outValue <= 8'b11100001;
4'h8: outValue <= 8'b00000000;
4'h9: outValue <= 8'b10000000;
default: outValue <= 8'b11101111;
endcase
end else begin
case (digit)
4'h0: outValue <= 8'b00110000;
4'h1: outValue <= 8'b11111001;
4'h2: outValue <= 8'b01010010;
4'h3: outValue <= 8'b11010000;
4'h4: outValue <= 8'b10011001;
4'h5: outValue <= 8'b10010100;
4'h6: outValue <= 8'b00010100;
4'h7: outValue <= 8'b11110001;
4'h8: outValue <= 8'b00010000;
4'h9: outValue <= 8'b10010000;
default: outValue <= 8'b11111111;
endcase
end
end else begin
pulseStep <= 0;
outValue <= 8'b11111111;
end
end
assign jd = outValue;
endmodule
Here is source of main design with basic demo of seven segment display. We are able to change brightness by 4 switch buttons sw[3:0] with following levels: 15,11,7,3. The default brightness level is set to 1.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 25.09.2018 21:02:57
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
input CLK100MHZ,
input [3:0] sw,
output [7:0] jd
);
reg [3:0] digit = 0;
reg dot = 1;
reg [3:0] pulseValue = 0;
display display(
.CLK100MHZ(CLK100MHZ),
.digit(digit),
.dotPoint(dot),
.pulseDuration(pulseValue),
.jd(jd)
);
reg [32:0] countReg = 0;
always @(posedge CLK100MHZ) begin
if (countReg < 99999999) begin
countReg <= countReg + 1;
end else begin
countReg <= 0;
if (digit < 9) begin
digit <= digit + 1;
dot <= 0;
end else begin
digit <= 0;
dot <= 1;
end
end
if (sw[3])
pulseValue <= 15;
else if (sw[2])
pulseValue <= 11;
else if (sw[1])
pulseValue <= 7;
else if (sw[0])
pulseValue <= 3;
else
pulseValue <= 1;
end
endmodule
Here is short video presentation of second version of display module:
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