Hi all,

I've seen quite a few recent posts with people seeing USB 2.0 speeds / connectivity when using the MPSoC.  I wanted to let you know that after scouring the interwebz, I think I've pooled enough information together to try to help you with your issues.

If you are already familiar with USB 3.0 and transceivers, you can skip to the end!  Or stick around, you might learn a thing or two!

As USB speeds have risen from the lowly 1.5Mbps to the great 5 Gbps that we see in today's SuperSpeed connectivity, we have to start to appreciate one thing that veteran FPGA developers had had to work with for years!

Transceivers!

UG576

Why transceivers?  Well, as speeds get higher and higher, you have to "get" that data from one point to another.  To do that, it makes sense to go wider and slower.  The problem is as time of flight gets smaller and smaller, your margin for getting all of the data lines to line up at the same time as the proper location of your clock or sampling trigger gets harder and harder.

(unrelated, but the image demonstrates lining up data with a sampler signal (clock in this case) - Xilinx Forums post)

People working with high data rates have long since known this and you see a LOT of data and signaling schemes to try to combat these issues.  One thing is clear, using an ANALOG signal to read our digitally encoded data in as FEW lanes as possible is the way to go with currently technology.

Alright, so what does all this have to do with USB 3.0 and the MPSoC?

Well, in high speed applications we start to have to worry about signaling MARGIN.  You can think of this as the "fuzzy" levels in our signal that can be interpreted as our data.  The more margin, the more room for error there is.  These can be seen as "eye diagrams".  As data is overlayed to a graph, you get a sense of just how much margin you have.  Larger centers of eye-diagrams are better, but too much is also bad.  There is a balance and every situation can be different.

This image taken from Tech Tips 104 - XILINX and IBERT  Video 4 Getting More Margin 2.  This is a series of training videos I produced a while ago.They teach you how best to tweak and tune transceivers on a Zynq-7000 based PicoZed.  The steps can be applied to just about any transceiver tuning.

Transceiver Tech Tips - Tuning Your Transceiver

Ok, Still, you have NOT mentioned the MPSoC!  Not even USB 3.0 related to it!

Right - so with that background knowledge, how does the MPSoC connect to USB?  For the Processing System (PS), it has two internal pieces of hardened IP.  One is the ULIPI USB 1.1-2.0 driver / transceiver, the other is the GTR based USB 3.0 IP.  GTR?  Didn't you mention GTH above?  I sure did!  The Xilinx Zynq-UltraScale+ MPSoC supports both GTH and GTR transceivers.  GTR is a special transceiver that has been used for supporting the Matrix of features the MPSoC's PS provides.  This includes Ethernet, PCIe, Display Port, and SATA.

Knowing that the USB 3.0 is a transceiver, that gives us a LOT of information about how this works.   Especially knowing that something is USB 3.0 is only half the story.  You then have to consider the TYPE of connector.  USB A, B, C, Standard, Micro, Mini.

https://en.wikipedia.org/wiki/USB

On most Xilinx reference boards which support USB 3.0, including the Avnet family, it was decided to continue using the USB A or B format connectors.

Type-A, Type-A SuperSpeed, Micro-B, Micro-B SuperSpeed, USB-C

(Images from above linked Wikipedia Link)

A cool thing to note and one of the reasons Micro-B SuperSpeed was chosen, the USB standard actually forces backwards compatibility!  As you can see, a USB Type A is Type A, but a SuperSpeed has added pins to allow the transceivers to link.  Same with Micro-B.

This means that for people that do not want to use USB 3.0, it provides an easy way to connect existing devices - without being FORCED to use a (at the time) expensive USB C type connector.

So where does all of this information leave us?  Eye-Diagrams, connector types, GTR transceviers...

Essentially, what I believe has been happening, people are running out of margin.  Without proper high quality cables, the eye is closing and we are seeing a loss of link, which then most (all?) USB 3.0 devices tend to drop back to USB 2.0.

I can say with personal experience that running a USB 3.0 webcam on an Ultra96V2, using it's USB-A SuperSpeed connector is possible and does work well.  I can also say that using a USB 3.0 webcam on an UltraZed-EV is also possible.  You just have to watch your signaling.  I have not had success using "cables" from EBay nor "sort by $ vs $$$" on other online stores.  I HAVE had success with a webcam that had a Micro-A SuperSpeed cable as well as using a HIGH Quality adapter such as the one from WhizzSystems.

If you search around the E14 forums, Xilinx support forums, or other places, you will likely see a few recommendations and I can say that I have actually used the WhizzSystems adapter.

[[You can now purchase the WhizzSystems adapter from the Avnet.com site, or your local sales office]]

AES-ACC-WHIZZ-USB3 (Link to Product Page)

USB 3 devices only detected with USB 2 speed  (post answered by my colleague)

You can also see people saying a Firefold adapter and a few others work well for them.

You can find links to those products in Kevin's post [note above link for easy access to purchase the WhizzSystems adapter].  We are currently working with a few suppliers to try to make these adapters more accessible.  Feedback I've received is that it is difficult to get these adapters.

If you have a specific need, please make sure to reach out to your support teams and we'll do our best to get you setup with the right hardware!

--Dan

**corrected spelling - supper is not support!
** added link to product - as of this posting, the product is active, but there is some missing data that I am working to fill in!