Spartan-6 VS Spartan-7 (7 Ways to Leave Your Spartan-6 FPGA : Comparison)

31 May 2022

Introduction:

Spartan-7 is the evolution of the older Spartan-6 series with improved performance, reduced power consumption and some new features. This evolution also addresses the problem of semiconductor shortage by incorporating the 28nm process technology.

This blog is in requirement with the 7 Ways to Leave Your Spartan-6 FPGA program. This blog will compare the Spartan-6 FPGA series with the new Spartan-7 series.

History:

The Spartan series targets low cost, high-volume applications with a low power footprint. Examples are displays, set-top boxes, wireless routers etc.

The Spartan-6 was first introduced in 2009. It is based on a 45nm, 9-metal layer, dual oxide process technology. It was marketed as a low-cost option for automotive, wireless communications, flat-panel display and video surveillance applications.

The Spartan-7 was announced in 2015 and launched in 2017. It is based on 28nm process and boosts the performance by 30% and consumes about 50% lesser power.

Comparison:

The table given below compares some basic features of the two series.

	Spartan-6	Spartan-7
Logic	There are three types of slices: Slice_M, Slice_L and Slice_X. Slice_X is the most basic one among these three.	There are two types of slices: Slice_M and Slice_L. The LUT in Slice_M can act as distributed memory. Functions implemented using a Slice_X can be easily accommodated within the Slice_L. Migration to Slice_L in 7 series devices can result in performance improvement. Retargeting of Slice_X to Slice_L is automatic in synthesis.
Block RAM	Block RAMs are arranged as 18Kb blocks. Can be configured as two 9Kb memories.	Block RAMs are arranged as 36Kb blocks. Can be configured as two 18Kb memories. Other improvements are built in FIFO, cascading block RAMs, built-in error correction codes.
DSP (Digital Signal Processing)	DSP48A1 provides 18x18 signed multiplication.	DSP48E1 provides 25x18 signed multiplication. DSP48E1 also enables the implementation of an ALU and enables support for Single Instruction Multiple Data (SIMD) mode. It is capable of implementing pattern detection and 17-bit shifter structures.
Clocking	Provides the developer with Digital Clock Managers (DCM) and Phase Locked Loops (PLL) clocking resources.	Provides the user with a simpler clocking architecture. Within a 7 series Clock Management Tile (CMT), MMCM and PLLs are provided and associated with each I/O bank.
Memory Interfaces	It uses an integrated memory block.	It uses a Soft IP core to implement the memory controller where only the memory PHY is hardened. This provides 7 series devices with a more flexible approach to I/O allocation and design Memory Interface Controller can support DDR3, DDR3L, DDR2, and LPDDR2 providing maximum flexibility in selecting the memory.
Transceivers and PCIe	Spartan-6 LXT devices provide the developer with multi-gigabit transceivers in the GTP at a maximum speed of 3.2 Gb/s.	Spartan-7 FPGAs don't have high speed transceivers.
Total I/O Count	Maximum 576 user I/O (in XC6SLX150).	Maximum 400 user I/O (in XC7S100).
Logic Cells	Maximum 147,443 logic cells (in XC6SLX150).	Maximum 102,400 logic cells (in XC7S100).
Flip Flops	Maximum 184,304 flip flops (in XC6SLX150).	Maximum 128,000 flip flops (in XC7S100).
DSP Slices	Maximum 180 DSP Slices (in XC6SLX150).	Maximum 160 DSP Slices (in XC7S100).
Total Block RAM (Kbits)	Maximum 4,824 (in XC6SLX150).	Maximum 4,320 (in XC7S100).
Static Power	Power consumed is more than that in the Spartan-7 series.	Spartan-7 FPGAs offer around 50% lower static power at nominal voltage and 70% lower static power at V-low.
Toolchain	Spartan-6 devices use the ISE, EDK, PlanAhead, and SDK tool chain. ISE uses the UCF format.	7 series use the Vivado and Vitis tool chains. Vivado uses XDC which are based on the SDC format. There is a huge improvement in design efficiency gained by using these new tools.
Additional Features	Spartan-6 doesn't have XADC.	XADC which is a dual 12-bit, 1 MSPS ADC which enables the developer to observe the internal supply voltages and die temperature. It also enables the Analog Mixed Signal (AMS) functionality. The XADC is also able to quantize 16 external differential signals, removing the need for additional low-speed ADCs used in board monitoring. Another new feature of the 7 series FPGA chips is the capability to encrypt the bitstream with 256-bit AES encryption and HMAC/SHA-256 authentication to protect from unauthorized copy of the design. The Spartan-7 also possess the capability of partial reconfiguration of modules in the programmable logic during operation.

Additional Points:

Logic:-Both the Spartan-6 and 7 series have a function generator which consists of a 6 input Look Up Table (LUT) with two associated flip flops. Several of these function generators and flip flop structures are combined to create a slice. Each slice contains 8 function generators and 16 flip flops.
Block RAM:- Block RAM is a dedicated RAM that does not consume any additional LUT in design whereas distributed Ram is built up with LUT. For most applications, the re-targeting should be automatic during synthesis. If, for example, there are many smaller memories like <9Kb, then a larger 7 series device capable of supporting that memory granularity may be required.
SIMD:- Single Instruction, Multiple Data (SIMD) units refer to hardware components that perform the same operation on multiple data operands concurrently.
DSP:- DSP slices satisfy high-performance signal processing tasks. DSP is used primarily in areas of the audio signal, speech processing, RADAR, seismology, audio, SONAR, voice recognition, and some financial signals. Mapping to the DSP48E1 from the DSP48A1 should be mostly automatic by the Vivado synthesis engine. However, to implement advanced modes such as SIMD, language templates are provided in the Vivado editor to allow ease of implementation to achieve the best performance.
PLL:- A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal.
DCM:- A digital clock manager is useful for manipulating clock signals inside the FPGA, and to avoid clock skew which would introduce errors in the circuit.
MMCM:- The Mixed Mode Clock Management (MMCM) module is used to generate multiple clocks with defined phase and frequency relationships to a given input clock.
Clocking:- Spartan-6 designs which use either a PLL or DCM_SP will migrate to a MMCM in a 7 series device. Clocking in Spartan-6 has different buffer types which determined connections and connectivity. While most other buffers (e.g., BUFH and BUFG) will migrate automatically during synthesis, buffers that are specific to Spartan-6 like BUFIO2 will need to be migrated in the design if directly instantiated in the design.
Power:- From the graph, it can be seen that the Spartan-7 FPGA offers lower static power as compared to the Spartan-6 FPGA. There are two different operating modes in Spartan-7 FPGA:
- High performance mode - The core voltage is 1.0V at lower static power.
- Low power mode - The core voltage is 0.95V and offers up to 70% lower static power.

Spartan-7 power advantage

Conclusion:

Spartan-7 is a lot more better in terms of power and performance. It also has some new interesting features like the XADC, encryption and partial reconfiguration capability. But still, it maintains its lower price as Spartan-6. Vivado provides the developer with significant design analysis and reporting for greater design insight. Migrating projects from Spartan-6 to Spartan-7 might need some work in some cases but above mentioned benefits balances the scale.

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