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  • Author Author: yesha98
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Summer of FPGAs - Building an Embedded System on FPGA

yesha98

Introduction:

Back then in February when I roadtested the USB104-A7, I had learned to create block designs using MicroBlaze. I found it very interesting but the available online resources were limited, the tutorials were based on the older versions of Vivado (Uploaded 6 years back or so). So I thought of making a course on using MicroBlaze in block designs and programming it with Xilinx SDK. Finally, after my semester exams were over, I got some free time to record the tutorials and the course material.

 

The course is designed in such a way that basic knowledge on FPGA programming using Vivado would be sufficient to take up this course. Also, the learner will understand the design of hardware while making the custom Pmod (Pmod Character LCD) and the working of Rotary Encoder.

 

Also, in this course, the design will be modified as new modules are added according to the requirements. The quadrature decoder module described in Verilog will also be added to the design at a later stage in the course. Thus, the learner will be able to feel the essence of the term "Reconfigurable Hardware".

 

Course Contents:

Video 1 - Introduction to MicroBlaze and AXI

Video 2 -- Lab 1 - Creating a block design with MicroBlaze and AXI GPIOs

Video 3 -- Lab 2 - Writing code in Xilinx SDK to interface with user LED and Pushbutton

Video 4 - Working of Character LCD and making of the Pmod LCD

Video 5 -- Lab 3 - Modifying the block design to interface Pmod LCD

Video 6 -- Lab 4 - LCD Driver Code to display elapsed seconds in LCD

Video 7 - Working of Rotary Encoder and Quadrature Decoder

VIdeo 8 -- Lab 5 - Adding the Quadrature Decoder Module to the Design

Video 9 -- Lab 6 - Writing code in SDK to display count and direction to the LCD

VIdeo 10 - Final Assessment

 

 

About the Course:

All videos are available on YouTube, here's the link to Playlist: https://www.youtube.com/playlist?list=PL6jYIySXv7VhUjg95oP88ubxRrr9MQMfH

Complete the final assessment to earn a certificate!

 

Course Overview:

 

Thanks for reading!

  • in reply to yesha98

      wrote:

     

    ... Also, just for clarification, the code written in SDK would work in Vitis also, right?

    Incidently, a topic of today's seminar:

    Ultra96-V2 Workshop: Session 3: Hello World on a Cortex-A53 and R5 Processor

  • in reply to Jan Cumps

    Thanks a lot, for trying it out and verifying the design.

    I appreciate it. Now that those who are trying Module 1 with Zynq will also be able to do it with ease.

     

    Thanks again for taking your time and trying this out! image

  • in reply to Jan Cumps

    Yes, as you mentioned, this design was intended for 7-series FPGAs like Artix-7 or Spartan-7.

    I'm planning to launch Module 2 which will be having Zynq as the SoC FPGA. 

  • in reply to Jan Cumps

    Works! Thank you.

    image

    The LaunchPad in the picture below is used to translate the UART 3V3 to a USB COM port.

    The Pynq-Z2 board configured in JTAG mode instead of Linux SD boot.

    image

     

    The debugger works too (note to anyone playing along: on a Pynq-Z2, move the top boot jumper from SD to JTAG. Do not populate the bottom jumper - that's to debug the PL):

    image

  • I'm at video 2, just finished the Vivado Block Diagram

    image

     

    I did 2 things different:

    • my board doesn't have a UART that can be connected to the PL, so I made the transmit pin external and will use a 3V3 serial to USB converter to get the data.
    • I used a util_vector_logic block to create a NOT gate instead of coding. The effect is the same.

     

    Validation works.

    I'm having errors synthesizing: [Common 17-217] Failed to load feature 'core'.

    That's because it's mandatory on the Zynq to place the PS ARM block.

     

    image

     

    So I changed the design a little specific for the Zynq on my board:

    • added the Zync, and used it for the clock and the reset (so that it does not have to do nothing image)
    • removed the clock wizard, because it's not needed, see step above.
    • still kept your reset, but used it as an additional one, for the PL blocks only.

    There is nothing wrong with your design, it's all because of the two ARM cores in my FPGA.

     

     

    In Vivado 2020.2, the menu to start Vitis (instead of SDK) has moved:

    image

     

    The startup is somewhat different. The hardware platform is not automatically loaded, but you can select the XSA exported from Vivado when creating an application project.

    Because of the Zynq FPGA I'm using, the ARM processors are also available for doing development on, next to the MicroBlaze

    image

    Then the result is more similar to the SDK look and feel:

    image