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Blog The Art of FPGA Design Season 2 - Post 11
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  • Author Author: fpgaguru
  • Date Created: 26 Jan 2021 3:48 PM Date Created
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The Art of FPGA Design Season 2 - Post 11

fpgaguru
fpgaguru
26 Jan 2021

The Single Rate Half-Band FIR Decimator

 

A decimating filter will reduce the sample rate of a signal, while preventing aliasing. Decimation by a factor of 2x is achieved by simply throwing out every second input sample. For this to work the input data must be first filtered and the upper half of the frequency spectrum attenuated to a point where it will not affect the desired signal after decimation. The half-band FIR is ideally suited for this task. We start again with the same single rate half-band FIR prototype filter, again illustrated here for the case where the filter order is N=11:

imageLike we did in the previous post, we start by separating the single rate half-band prototype filter into two branches, one even and one odd:

Since we plan to drop every second output sample, we only need to consider even input samples going through the first branch and odd input samples through the second branch, which contribute to the even output samples that we will keep. There is no need to consider odd input samples through the first branch and even input samples through the second branch because these only contribute to odd output samples, which do not need to be calculated. Also, every pair of delays in both branches is replaced with a single delay: image

imageWe can recognize again the same structure we have seen in the interpolator case, just connected in a slightly different way. We still have two filter branches, one a pure delay and the other one an even-symmetric single rate FIR. We already have efficient implementations for the later, so this is how a direct half-band decimator would look like for the case when N=19:

image

Note that there is no need for a final fabric post-adder, we achieve the same result by injecting the even input samples at the entry point of the adder chain, with a proper delay. A transposed implementation is of course also possible:

The transpose version is more efficient, with lower latency but limited scalability beyond about 20 taps. This problem can always be addressed by inserting extra pipeline registers. image

 

Like it was the case with the half-band interpolating FIR, a half-band decimator is 8x more efficient in terms of multiplications per output sample than the direct, naïve implementation of the mathematical algorithm. We get a 2x improvement if we take advantage of the prototype filter symmetry and another 2x factor for not computing multiplications with coefficients that are zero. Finally, since we do not need to compute output samples that we will then throw away through decimation, we have another 2x efficiency factor.

 

Next we will go back to single rate FIRs, where the input sample rate is equal to the output sample rate, but will consider the case when this sample rate is different from the hardware clock frequency.

 

Back to the top: The Art of FPGA Design Season 2

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Top Comments

  • fpgaguru
    fpgaguru over 5 years ago +2
    Hi Rod, There are three main ways you can do DSP hardware design with FPGAs. 1. Classic HDL design flow, using either Verilog (or rather SystemVerilog) or VHDL 2. With SysGen, which requires Matlab and…
  • drozwood90
    drozwood90 over 5 years ago in reply to 14rhb +2
    Hi there, In older versions of the tools, you needed to have the HLS version installed + licensed. I would suggest that if you have a webpack supported board, upgrade to the 2020.2 tools using Vitis. There…
  • fpgaguru
    fpgaguru over 5 years ago in reply to 14rhb +2
    Hi Rod, I hope you meant 2020.2, not 2012.2. I think that Vitis/Vivado 2020.2 would be the right tool flow for you to use. Catalin
  • 14rhb
    14rhb over 5 years ago

    Hi fpgaguru

     

    Your latest post was very timely as I have been looking (and failing) at DSP under my roadtest USB104 A7: Artix-7 FPGA Development Board  : although a complete beginner I found the topic very exciting and will be reading your series of reports closely to see what I can create. You mention in one of your posts you undertake this work yourself but have links to Xilinx and you may be best placed to help me understand a few very basic issues. As a hobbyist I'm using the free software (although I do have a Xilinx license for Vivado that came with a higher specification board).

     

    Is the only way of credibly configuring the DSP slices to use Xilinx System Generator and Simulink ? I see some of the IP I do have available such as IIR and FIR Compiler use the DSP48 slices.

     

    Without wanting to get you in trouble, are you aware of any open source approaches ? There seems to be several contenders for testing out the DSP algorithms such as Octave, R-Studio maybe, Scibus. I guess the missing part is creating a verilog script from those packages that makes use of the DSP slices in the 7-series FPGAs ?

     

    As mentioned, I'm a novice here but pointers to material would be greatly appreciated to allow me to experiment with these powerful devices.

     

    Thanks

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