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Blog Migrate the Digilent XADC demo (to Vivado 2020.2)
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  • Author Author: Jan Cumps
  • Date Created: 24 Jun 2022 10:55 AM Date Created
  • Views 1566 views
  • Likes 9 likes
  • Comments 3 comments
  • summer_of_fpga
  • Spartan_Migration
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Migrate the Digilent XADC demo (to Vivado 2020.2)

Jan Cumps
Jan Cumps
24 Jun 2022
Migrate the Digilent XADC demo (to Vivado 2020.2)

Digilent has a set of demo projects for the Arty board. I'm reviewing Arty XADC Demo. I'm going to make a project with an analogue sensor, and that project is a good starting point.

Migrate the Demo from 2016.4

The demo was written for Vivado 2016.4. Migrating to a newer version (in my case: 2020.2) isn't hard. Follow the instructions, but do these corrections before and after project creation.

Before running the create script:

The script uses an older board version, that's not available if you use Digilent's instructions to install board files. Change the script:

# set brd_part "digilentinc.com:arty-s7-50:part0:1.0"
set brd_part "digilentinc.com:arty-s7-50:part0:1.1"

After script execution

The xadc wizard IP is changed. Vivado locks it, and you can't continue unless you remediate. In this case, you upgrade the IP:
image
Select the convert option, confirm next dialogs.
image

Once this is fixed, Vivado will run the implementation.
image

Run the demo

Generate the bitstream and program the device as usual. When you set the 4 switches to the lower position, Arduino input A0 is active and can accept 0 - 3V3 values. 
image
The higher the voltage, the more LEDs will turn on (order LD2 -> LD4 -> LD0 -> LD1).
I attached an LDR circuit to the input.
image
Here's the result:

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  • Jan Cumps
    Jan Cumps over 3 years ago

    Related: Migrate the Digilent Arty S7-50 General I/O Demo (to latest board file)

    Download the latest release full project archive and extract it. Before opening it in Vivado, edit Arty-S7-50-GPIO.xpr

    # <Option Name="BoardPart" Val="digilentinc.com:arty-s7-50:part0:1.0"/>
    <Option Name="BoardPart" Val="digilentinc.com:arty-s7-50:part0:1.1"/>

    Open the project, generate bitfile, program, enjoy

    image

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  • Jan Cumps
    Jan Cumps over 3 years ago

    XADC tip (works on a Zynq too):
    Via the hardware manager, you can always check the device's XADC values. No matter what design is running (or not) running) on the FPGA.

    image

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  • Jan Cumps
    Jan Cumps over 3 years ago

    This project show how to use Vivado without block diagram or HDL wrapper. It's a single source Verilog design.

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