Barriers to designing with FPGAs?

Here’s what I see as the main barriers to getting people to play with FPGAs.

1.  “Logic!  Why don’t they teach logic in these schools?” asks the Old Professor in The Lion, the Witch, and the Wardrobe.  Well, they didn’t teach logic when I was in USA schools.  It was something you had to learn on your own.  I see no evidence that they’re teaching it now.  I don’t know about other countries.

Schools teach algebra, so you’re in better shape for computer programming.  But symbolic logic is the basis of FPGA design, so if you have to learn it at the same time that you’re trying to absorb the rest of FPGA design the learning curve is that much steeper.

2.  Verilog and VHDL are pretty much the only game in town for designing FPGAs.  The problem is that both are languages for describing hardware behavior and rather than the hardware itself.  If you’re an accomplished hardware designer, you know what registers and memories you want and what logical and arithmetic functions you want.  But to get a synthesizer to generate that hardware you have to write your Verilog or VHDL in just the right way so that the synthesizer recognizes pre-defined patterns for edge-triggered registers, clocked latches, and memories.  If you get the pattern wrong, the synthesizer will try to implement what you wrote but it will likely be a mess.  It’s usually hard or completely impractical to look at the netlist generated by the synthesizer so good luck untangling it.  If you’re a new designer, fuggeddabouddit.

At Design West / ESC 2013, Duane Benson gave a terrific talk called “FPGAs: I know nothing... yet” which covered a number of the challenges a new FPGA designer faces with Verilog.  It’s a great talk if you can find it online somewhere.  We had a recent discussion here at element14 called Connecting Verilog to Synthesis.  The OP had a design that simulated just fine but there were all sorts of problems when he tried to synthesize.  They can be very frustrating and discouraging for new users.

Here’s another recent example, this one from Gadget Factory: VHDL newbie: 'if' on a process sensitivity list element.  This new designer left some logic unspecified which caused the VHDL synthesizer to change combinational logic to clocked logic, and then gave an obscure error message about the user’s clock (which he didn’t realize he had).  VHDL calls every variable a signal and figures out at compile time which are combinational and which are registers, so if you make a mistake you can suddenly have unexpected added or missing registers.  In Verilog, you declare a variable as a wire or reg, which usually (but not always) prevents this particular problem.

I think those two discussions do a great job of illustrating the learning curve problem for VHDL and Verilog.

3.  FPGA tools have a steep learning curve.  If you want to write a C program, you start with “Hello, world” which is two lines of source code.  It takes one GNU command to compile it and one to execute it.

If you want a simple blinking light on an FPGA, you’re faced with the very long process of downloading the FPGA tools, getting the license manager to let you run the tools, figuring out how to use the tools, finally getting an FPGA bitstream, and writing it to your development board.

Plus the code itself is a lot more involved.  Blinking an LED sounds easy, but remember that your development board probably has a 32MHz or 50 MHz oscillator, so you need a clock divider to get it down to a few Hz.  Suddenly you need to learn about sequential logic and always or process statements.

We’re talking orders of magnitude more work than “Hello, world”.  OTOH, getting an LED to blink on a Raspberry Pi or BeagleBone is pretty involved too

Is there a better way?  You bet -- take a look at the examples at the end of Flavia: the Free Logic Array.

johnbeetem wrote:

 

3.  FPGA tools have a steep learning curve.  If you want to write a C program, you start with “Hello, world” which is two lines of source code.  It takes one GNU command to compile it and one to execute it.

 

If you want a simple blinking light on an FPGA, you’re faced with the very long process of downloading the FPGA tools, getting the license manager to let you run the tools, figuring out how to use the tools, finally getting an FPGA bitstream, and writing it to your development board.

 

Plus the code itself is a lot more involved.  Blinking an LED sounds easy, but remember that your development board probably has a 32MHz or 50 MHz oscillator, so you need a clock divider to get it down to a few Hz.  Suddenly you need to learn about sequential logic and always or process statements.

 

We’re talking orders of magnitude more work than “Hello, world”.  OTOH, getting an LED to blink on a Raspberry Pi or BeagleBone is pretty involved too

 

Is there a better way?  You bet -- take a look at the examples at the end of Flavia: the Free Logic Array.

In my continuing Quixotic quest towards making it easier for people to get started with FPGAs, the new release of Flavia (XXICC rev 0.0n) supports the ValentF(x) LOGI-Pi and LOGI-Bone.  Both boards have a Spartan-6 LX9 FPGA.

johnbeetem wrote:

 

3.  FPGA tools have a steep learning curve.  If you want to write a C program, you start with “Hello, world” which is two lines of source code.  It takes one GNU command to compile it and one to execute it.

 

If you want a simple blinking light on an FPGA, you’re faced with the very long process of downloading the FPGA tools, getting the license manager to let you run the tools, figuring out how to use the tools, finally getting an FPGA bitstream, and writing it to your development board.

 

Plus the code itself is a lot more involved.  Blinking an LED sounds easy, but remember that your development board probably has a 32MHz or 50 MHz oscillator, so you need a clock divider to get it down to a few Hz.  Suddenly you need to learn about sequential logic and always or process statements.

 

We’re talking orders of magnitude more work than “Hello, world”.  OTOH, getting an LED to blink on a Raspberry Pi or BeagleBone is pretty involved too

 

Is there a better way?  You bet -- take a look at the examples at the end of Flavia: the Free Logic Array.

In my continuing Quixotic quest towards making it easier for people to get started with FPGAs, the new release of Flavia (XXICC rev 0.0n) supports the ValentF(x) LOGI-Pi and LOGI-Bone.  Both boards have a Spartan-6 LX9 FPGA.