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Project IceStorm: fully open-source FPGA tools for Lattice iCE40

johnbeetem

As some of you may have noticed, I've been obsessed for many decades with having open FPGA bitstream documentation so that people can write their own FPGA designs tools, especially FLOSS (Free-as-in-Liberty Open Source Software).

 

I recently found out about IceStorm, a project that has somehow reverse-engineered and documented the Lattice iCE40 FPGA.  They've actually put together a fully-open-source tool chain with Yosys for Verilog synthesis and Arachne_pnr for placement and routing.  I don't know how usable or robust the tools are.  I'm planning on taking a close look starting next month.

 

If you're interested, here's the IceStorm link, which has links to the other tools: Project IceStorm

Discussion of Yosys and the tools is at reddit: Yosys Open SYnthesis Suite

 

Update: Here are a couple of nice Hackaday items about IceStorm:

 

From 29 March 2015: Reverse Engineering Lattice’s iCE40 FPGA Bitstream | Hackaday

From 29 May 2015: An Open Source Toolchain For iCE40 FPGAs | Hackaday

 

Update 2: Here are some good IceStorm installation instructions: Projet IceStorm : le FPGA libéré ! | Front de Libération des FPGA.  They're in a combination of French and GNU/Linux.

 

Here's the Lattice IceStick directly supported by IceStorm: Lattice Semiconductor: ICE40HX1K-STICK-EVN iCEstick Evaluation Kit.  It's US$20.89 in the USA.

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  • I'm amazed and impressed at the amount of effort going into this but for so little gain !

     

    Targeting the 1k part and no support for block ram or plls isn't really getting to the point where you could do any real design with the tools so the project has a very long way to go.

     

    From a personal point of view it's such a shame they are using Verilog 2005  - which is a pretty low base for an HDL.

     

    If it ever gets to the point of supporting the bigger iCE40 parts the packages will be a problem - some of the newer ones come in 0.5mm pitch BGA (or smaller if you like image).

     

    MK

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  • I'm amazed and impressed at the amount of effort going into this but for so little gain !

     

    Targeting the 1k part and no support for block ram or plls isn't really getting to the point where you could do any real design with the tools so the project has a very long way to go.

     

    From a personal point of view it's such a shame they are using Verilog 2005  - which is a pretty low base for an HDL.

     

    If it ever gets to the point of supporting the bigger iCE40 parts the packages will be a problem - some of the newer ones come in 0.5mm pitch BGA (or smaller if you like image).

     

    MK

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  • in reply to michaelkellett

    Michael Kellett wrote:

     

    I'm amazed and impressed at the amount of effort going into this but for so little gain!

    I see IceStorm as a huge step in the right direction.  IMO the best way to get vendors to document their bitstreams is to have projects like IceStorm and my Flavia show that it's possible to use FLOSS tools and that there are advantages to doing so, both for users and vendors.  For example, Flavia is much faster than Xilinx tools for small designs, making it a better platform for teaching programmable logic concepts.  I'm hoping these projects will embarrass Xilinx and Altera into opening their bitstreams.

     

    I'm looking forward to playing with IceStorm.  While the iCE40 HX1K is indeed a small part, it's big enough for teaching about FPGAs and has a lot more capacity than any of my Flavia implementations.  So it looks like a good answer to 's FPGA/CPLD education question: http://www.element14.com/community/thread/17692?start=56

  • in reply to michaelkellett

    Just FYI:

     

    14 months on - now icestorm supports ice40(hx/lp)[1,4,8]k, in all packages, including the PLL's and embedded block srams.

    There's a timing analysis tool too, and one for replacing sram images within bitfiles without recompiling.

     

    All the tool install, compile and run happily on ARM SBC's in 32 and 64 bit flavours, and even in Mac OS X - AFAIK the only FPGA toolchain to work natively within those.

    (although you will want at least 512MiB ram to run the toolchain on 8k designs without dipping into swap).

     

    Given that the tools will run on a $5 RasPi Zero, and a fair few of the new development boards coming out support the RasPi's 40 pin connector, this makes it possible to have a low cost, embedded, and very high performance (due to the fpga logic) control system which can inexpensively be deployed whilst actually including all it's own documentation and locally hosted development tools.

     

    And that's an entirely new capability - and certainly a gain!