FPGA Design Consideration

Question

Hi, I'm very new to FPGA. Most of what I did was PIC and Atmel microcontrollers. I want to know about the design consideration of implementing an FPGA into a system. How do you pick the suitable FPGA to suit your needs? I know there are specifications such as number of logic elements, PLLs, multiplier and such but you will never know how much of those you will need until you finish the vhdl and compile it. Correct me if I'm wrong but I'm pretty sure the hardware has to be finalized before the vhdl codes are done in a general development process.

Also, I see that there are a few companies making FPGA. Namely Xillinx, Altera, Lattice etc. What are the differences between their product? Most of what I can search online talks about their development IDEs in terms of which one has free tools or which company has IP restrictions. It's hard for a beginner like me to make sense of what Cyclone offers compared to Spartan and such.

Third question is how do you objectively quantify and compare the performance between FPGAs? Assuming they all run at the same clock. Since they are all essentially doing the same thing and is functionally the same when loaded with the same vhdl code. How do they fare against each other in terms of efficiency, speed and what not? Googling around I only find people comparing them with GPUs and CPUs. Companies advertising their product using vague and very general descriptions doesn't help at all.

Sorry if these are very newb questions but I am a newb trying to learn FPGA. My college provides FPGA courses which I am now just starting but they only teach how to write vhdl. There are no info on hardware considerations or even how to set up a FPGA chip. Thanks in advance!

johnbeetem · Answer

That's a lot of material to cover, but I'll try to tackle a few items. First, it's unfortunate that your college only does VHDL. I personally prefer Verilog, which is more concise and IMO easier to write and understand. Verilog is based on C. VHDL is based on Ada. Second, there's a huge spectrum of FPGA offerings so which you choose depends on what you want to do and how much money you want to spend. There are cheap ($1 or a few dollars) FPGAs from Lattice -- e.g., the iCE40 family -- with a small number of look-up tables (LUTs). They're a good alternative to CPLDs, which are now a "mature" technology. Small FPGAs are good for "glue" logic and various specialized communication interfaces. Then you have mid-priced ($10s of dollars) FPGAs from Xilinx (Spartan) and Altera (Cyclone), with enough logic, RAM, and arithmetic to do amazing things. I've mostly used Xilinx and it's my preference at this level. Then you have expensive FPGAs ($100s to $1000s of dollars) from Xilinx and Altera. These are mostly for highly-specialized applications like signal/image processing and cryptography that can afford chips like these. I've always been able to fit customer applications into Spartan chips by using logic resources efficiently. Xilinx salesmen don't like me. When I do an FPGA design for a customer, I want to use the cheapest FPGA that will do the job. However, I also realize that the customer's needs may change and they'll want to do much more with the same hardware, so I choose an FPGA family and package that has a range of FPGA capacities in the same package. Xilinx Spartan tend to do this well. To make sure everything fits, I do a preliminary design and synthesize it to make sure it fits the logic and RAM capacity of the FPGA and meets the clock cycle constraint. Sometimes it's necessary to pipeline a design to meet the clock cycle. I far prefer to use a relatively slow clock -- say, 33-40 MHz for a Spartan-3A or Spartan-6 -- so that I can fit many levels of logic into a single clock cycle. For people who are just starting out and want to play with FPGAs without investing much money, I strongly recommend Lattice's iCEstick , which is available in the USA for as little as $22 (though for some reason element14 has it listed for $30, with none available). A unique feature of the Lattice iCE40 FPGA on iCEstick is that it can be programmed using open-source tools: http://www.element14.com/community/thread/43876/l/project-icestorm-fully-open-source-fpga-tools-for-lattice-ice40 . The tools support Verilog rather than VHDL. If you have more money to spend, I recommend Gadget Factory's Papilio boards and ValentF(x) LOGI-Pi and LOGI-Bone. They bring out lots of I/O and some of the boards have external SRAM or SDRAM. FPGA software and chip interfacing have steep learning curves. I recommend using an existing board like iCEstick or Papilio so you don't need to consider details like how to configure FPGAs. The Xilinx and Altera design software packages are huge and will take a lot of time to get working. There are tutorials out there -- Gadget Factor is a good place to start. The open-source IceStorm for Lattice iCE40 has a much simpler learning curve, but has minimal documentation. You'll need a GNU/Linux box with a GCC compiler that supports C++11 to compile and run the IceStorm tools.

jc2048 · Answer

This is an interesting thread and I'd like to add a few (rather random) thoughts. Note, though, that I haven't done anything with FPGAs for about 5 years now, so some of this may be a bit out of date. I worked with Spartan 3 parts using VHDL. Speed. The headline speed on the datasheet is for a very simple counter. You won't create a real design to operate that fast. The way to get a feel for the realisable speeds you can achieve is to knock up some trial designs and look at the max clock speed that gets reported. It's not easy to give you an guide because it depends so much on how you code and how well that maps onto the hardware, the nature of the design and what you're trying to do, how much of the device resources you're using, and so on. The DL in VHDL stands for Description Language. You are describing the hardware. You really do need to understand the underlying hardware to code efficiently. If you approach it as a simple programming exercise you'll end up with very bloated designs that only run slowly. Watch out for implied memory. Once you've done a few designs, you'll find that you can go a long way on cut-and-pasting. I got so that my start point for a new design was generally something I'd already done that was similar. The synthesis software works very efficiently if the design is sparse [say up to 50%-60% utilisation of resources], but as you cram more and more into your design you'll find it gets harder and harder for it to complete, even though in theory there are resources still available. If you are working commercially, and don't need to shave every last penny off your costs but do need to get designs out quickly and efficiently, give yourself plenty of capability in hand. One nice feature of the Spartan parts was having 2 or 3 different densities of device available in the same footprint package - knowing that there was a higher density device available that could go on my board was reassuring early on when I wasn't very confident about estimating the logic and memory resources that I would need. Constraints (timing and placement) seem like a good idea but can be counterproductive. I had a design where I needed a very small part of my design to operate very quickly. I tried tying down the logic blocks concerned and put timimg constraints on the signals and it always did worse than the unconstrained synthesis. The programmers at Xilinx knew their chips much better than I did and me tying them down was just getting in the way. [But do experiment - that's the kind of thing that can change or you might have a flair for it that I don't] The Xilinx design software has a viewer to show you how the synthesis has arranged everything internally. Use it as you gradually build up a design and you'll get a feel for how the synthesis places everything. It will also show you [with a bit of experimentation on your part] how to organise your IO pins to best work with your internal logic and minimise timing delays. The block RAMs in the Spartan parts turned out to be very useful [though as John Beetem says you're making your design less portable]. Table look-up is very fast - I used them for gamma correction, amongst other things. The RAM can be loaded from configuration data to give a ROM, too, though I usually used the second port to load the table values from an external processor. They were also useful for moving between clock domains [several of the products I worked on involved taking DVI from a computer and processing it, and the dual-port block RAMs enabled me to set up a swinging buffer with different clocks on the two sides].

Jan Cumps · Answer

On the tutorial part, there's also the very good VHDL handbook (and a list of FPGA projects he did, with source code) from hamsternz . FPGA course - Hamsterworks Wiki! I'm using a jack.gassett 's Papilio Pro ( Papilio FPGA Platform ) as my FPGA training board. devbisme2 's Xula and Xula-2 are also excellent: http://www.xess.com/

FPGA Design Consideration

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