How should I modify the constraints file for clock?

Its because pins have PACKAGE_PIN properties like AA1 or W15.

In the original constraint the pins are AD11 and AD12, look up the package references for the pins you want to use (and they will be similar to A1 B2 etc)  and put them in the constraint.

If you use the pin editor to generate the constraint it won't let you do wrong things. I'm not sure that LVDS is  a valid IOSTANDARD.

What board are you using ?

MK

Hi.  I am still new to FPGA, so don't mind my ignorance.  I went through the user guide for KC705 and found this for AD11 and AD12.

And then I went through this https://www.xilinx.com/support/documentation/user_guides/ug475_7Series_Pkg_Pinout.pdf  and found this:

I thought that the pin definitions were similar and hence changed them.  I changed the IOSOURCE based on a few readings.

The part number for my FPGA is XC7k160tFBG676-2.  Unfortunately, I don't know the board.  But it belongs to the 7 series.

Thank you.

On page 57 of that document it tells you about the ASCII pinout files. You need to download one of these and look at it with Excel. You need the schematic diagram of your board. From the schematic you can work out which pins the clock is connected to and the voltage at which the IO pins must be programmed to operate.

Are you a student or is this for commercial work ?

If  student then grab a tutor and ask a lot of questions, if commercial get your boss to send you on a Xilinx course - you'll learn as much in 1 week of a course as you will in 4 of experimenting so it will pay back.

MK

Thanks for the help MK.  I am currently an intern, so neither of the options apply to me.  I did dig around.  Found the schematics as per your advice and changed the pins to Y23 and AA24.  Worked.

Rachit Ajitsaria wrote:

 

Thanks for the help MK. I am currently an intern, so neither of the options apply to me. I did dig around. Found the schematics as per your advice and changed the pins to Y23 and AA24. Worked.

Presumably as an intern you are not just left to your own devices, you must have a team leader or somebody to oversees what you are doing? They should be able to help you so ask them lots of questions just as you would a tutor at college. If there isn't anybody else there to help you then I think the 2nd option still applies, if the company wants an intern to do this work then they should consider training requirements and factor in this cost.

Anyway, I'm glad michaelkellett was able to help you out and you've got this issue solved. Good luck with the rest of your project.

Best Regards,

Rachael

Happy it worked - I'm not so far ahead of you on Xilinx - I've been using Lattice parts and tools for years (the last 10 or so) but just started (March) a big project moving one customer over to Xlinx and Vivado. It's quite hard getting used to a very different way of working.

MK

Thanks Rachel.  My advisor is very helpful, but cannot be present with me all the time.  So I need to figure things out or else I will have a very low productive day.  Thanks again.