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A 3.3v (or less!) issue.

YT2095

How does one get around this problem in Design?

all My MCUs are 5v I/O, as are the CPUs and other peripheral ICs that I`d be interested in using with CPLDs, so any Gain in board real-estate and lower power consumption, would be taken away by having to use Level Translator ICs.

 

is this just the harsh reality, or there a workaround at all?

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    1.  If you're using CPLDs rather than FPGAs, you could go with a CPLD family that has 5V-tolerant I/Os such as the Xilinx XC9500XL series.

     

    2.  Usually you can drive 5V inputs with 3.3V outputs, so it's usually not a problem for inputs of 5V devices.

     

    3.  Some 3.3V FPGAs such as the Xilinx Spartan-IIE do not have 5V-tolerant inputs per se, but as long as you keep the input current low enough you can connect 5V outputs through (say) 1K Ohm resistors, assuming the resistors don't slow things down too much.  This may take care of some 5V outputs.

     

    4.  Otherwise you do need level shifters or use N-FET bus switches as voltage limiters.

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  • 0

    1.  If you're using CPLDs rather than FPGAs, you could go with a CPLD family that has 5V-tolerant I/Os such as the Xilinx XC9500XL series.

     

    2.  Usually you can drive 5V inputs with 3.3V outputs, so it's usually not a problem for inputs of 5V devices.

     

    3.  Some 3.3V FPGAs such as the Xilinx Spartan-IIE do not have 5V-tolerant inputs per se, but as long as you keep the input current low enough you can connect 5V outputs through (say) 1K Ohm resistors, assuming the resistors don't slow things down too much.  This may take care of some 5V outputs.

     

    4.  Otherwise you do need level shifters or use N-FET bus switches as voltage limiters.

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