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Forum Vivado and Zynq: TRI-STATE help
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  • zynq
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Related

Vivado and Zynq: TRI-STATE help

Jan Cumps
Jan Cumps over 3 years ago

I'm trying to write i2c code for Zynq, in VHDL.
I have difficulties creating a TRI-STATE pin.

The output logic should be: the pin is either pulled down to 0, or open-collector.
I have a pull-up resistor between that pin and VCC (3.3 V).
I'm expecting that if I write '0', it is low. When I write 'Z', it's open collector and pulled high by my pullup.
But in my design, the pin stays low. 0.62 V.

I thought, from reading up, that I should be done by:

  • defining the pin as INOUT
  • when you want to drive it low, assign '0'.
  • when you want to drive it open collector, assign 'Z'.
  • put an external pullup between pin and VCC

I created a testbed that puts the pin in "Z' mode, except when reset is asserted (via an external button).
In my testbed I also added a test pin, that I attach to an LED, that is high when the reset is asserted.
I connected a multimeter to the output.

The LED behaves as expected. It lights up when I assert the reset.
But the tri-state pin stays low, whether I write '0' or 'Z' to it. 

entity tristate_test is
    Port ( 
    reset_n: in std_logic;
    reset_out: out std_logic;
    tristate_pin : inout std_logic);
end tristate_test;

architecture Behavioral of tristate_test is

begin

reset_active: process (reset_n) is

begin
  if (reset_n = '0') then
    tristate_pin <= '0';
    reset_out <= '1';
  else
    tristate_pin <= 'Z';
    reset_out <= '0';
  end if;
end process reset_active;

end Behavioral;

Here is how I set the constraint:

image

set_property PACKAGE_PIN Y18 [get_ports tristate_pin_0]
set_property IOSTANDARD LVCMOS33 [get_ports tristate_pin_0]
set_property DRIVE 12 [get_ports tristate_pin_0]

Schema:

image

PMOD A pin 1 is PACKAGE_PIN Y18

What am I doing wrong?

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  • jc2048
    jc2048 over 3 years ago +4
    It might be a problem with hierarchy with the drag-and-drop stuff. An answer to this support question suggests that you need to set the synthesis to flatten the hierachy so that the tristate-ness can propagate…
  • jc2048
    jc2048 over 3 years ago in reply to bhfletcher +4
    Once you understand that the block-based design is an entity that could be used as part of a larger, more traditional design, the issue with the top-level wrapper becomes clearer. If the user is just using…
  • rachaelp
    rachaelp over 3 years ago +3
    Hi Jan, Just create the tristate in an assignment and not in a process. Not sure why what you have isn't working, have you looked at the schematic for what it's creating in Vivado? I guess maybe it's…
Parents
  • jc2048
    0 jc2048 over 3 years ago

    It might be a problem with hierarchy with the drag-and-drop stuff. An answer to this support question suggests that you need to set the synthesis to flatten the hierachy so that the tristate-ness can propagate up from the block to the actual IO pin.

    https://support.xilinx.com/s/question/0D52E00006iHuBxSAK/tristate-logic-not-implemented-in-20164?language=en_US

    My interpretation of that is, what you're describing in the VHDL actually implies an internal tristate line from the block to the output driver, but, if you tell the synthesis to flatten everything, it then fudges things for you so that it's the output pin getting controlled.

    An alternative approach to inference, if you can't make that work, is perhaps to try instantiating an IOBUF component. Page 203 of this 7-series guide shows how to do it from VHDL.

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf

    (Is your Zync a Zync-7000, or is it something else? If it's something else, you'll have to look for another document.)

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  • jc2048
    0 jc2048 over 3 years ago

    It might be a problem with hierarchy with the drag-and-drop stuff. An answer to this support question suggests that you need to set the synthesis to flatten the hierachy so that the tristate-ness can propagate up from the block to the actual IO pin.

    https://support.xilinx.com/s/question/0D52E00006iHuBxSAK/tristate-logic-not-implemented-in-20164?language=en_US

    My interpretation of that is, what you're describing in the VHDL actually implies an internal tristate line from the block to the output driver, but, if you tell the synthesis to flatten everything, it then fudges things for you so that it's the output pin getting controlled.

    An alternative approach to inference, if you can't make that work, is perhaps to try instantiating an IOBUF component. Page 203 of this 7-series guide shows how to do it from VHDL.

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf

    (Is your Zync a Zync-7000, or is it something else? If it's something else, you'll have to look for another document.)

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  • Jan Cumps
    0 Jan Cumps over 3 years ago in reply to jc2048

    I had read about the flat levels and the IOBUF too. I wasn't able to find how to do these in Vivado. I'm going to check the resources you linked.

    The tri-state pin isn't on the top level in my case. It's inside the VHDL of the i2c IP that I placed on that top level. Off to the manual...

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  • Jan Cumps
    0 Jan Cumps over 3 years ago in reply to jc2048

    I've tried the "flatten hierarchy" option. 

    image

    Re-synthesised and implemented. No success.
    checking further ...

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