hi all,
i'm having a problem for implementing an i2c bus with zynq7020 in vivado2018 in a block design structure.
i have read many notes for implementing the tristate signal in vivado. the synthesis option is global. the signal is in the top level and the tri state buffer also created in schematic ( the picture is attached). also i have tried flatten hierarchy in settings. the port is inout and the pull up resistors are available in hardware design. the assignment are out of any process.
the problem is that when 'Z' is assigned to my SDA port, it starts toggling continuously with no reason . the same code works in ISE so i am sure about the hardware design.
what am i doing wrong?
thanks for advices