Actions
Forum Thread Details
  • State Not Answered
  • Replies 2 replies
  • Subscribers 549 subscribers
  • Views 1602 views
  • Users 0 members are here
Related

i2c bus in zynq

MRP4695

hi all,

i'm having a problem for implementing an i2c bus with zynq7020 in vivado2018 in a block design structure.

i have read many notes for implementing the tristate signal in vivado. the synthesis option is global. the signal is in the top level and the tri state buffer also created in schematic ( the picture is attached). also i have tried flatten hierarchy in settings. the port is inout and the pull up resistors are available in hardware design. the assignment are out of any process.

the problem is that when 'Z' is assigned to my SDA port, it starts toggling continuously with no reason . the same code works in ISE so i am sure about the hardware design. 

what am i doing wrong?

thanks for advicesimage 

Parents
  • 0

    Hi,

    I have used tri-state with block design. First, you need to create some driver for io operations, like there is no inout type. So you should have, if I remember correctly, something like this:

    module something(input in_tri_i, output out_tri_o, output state_tri_t)
    //This _tri_x should infer tristate interface definition for block design.
    //if not try adding Xinterface info for tristate definition.
    //Write some module like there is no tristate ports
endmodule

    Then I have exported this interface tri-state as output interface for my block design (right mouse click on ip -> make external). With this approach, there should be no need for changing synth options to "global".  

    For changing "Z" state, check Vivado warnings. Maybe something is optimized out?

Reply
  • 0

    Hi,

    I have used tri-state with block design. First, you need to create some driver for io operations, like there is no inout type. So you should have, if I remember correctly, something like this:

    module something(input in_tri_i, output out_tri_o, output state_tri_t)
    //This _tri_x should infer tristate interface definition for block design.
    //if not try adding Xinterface info for tristate definition.
    //Write some module like there is no tristate ports
endmodule

    Then I have exported this interface tri-state as output interface for my block design (right mouse click on ip -> make external). With this approach, there should be no need for changing synth options to "global".  

    For changing "Z" state, check Vivado warnings. Maybe something is optimized out?

Children
No Data