Migration from the Spartan-6 to the Spartan-7 FPGAs brings about improvements, but it would be interesting to find out which roadmap is preferable by developers. Here is the choices,
- Design Baremetal with simple Flip-Flops in Block Design in VIvado
- Design Baremetal with IP integrator in Vivado
- Design Baremetal with Verilog , System Verilog or VHDL in Vivado
- Designing with MicroBlaze only in Vivado
- Desiging with C++ code in Vitis
Refer the the blog Build a project with the Arty S7-The Blinky Project - Blog - FPGA - element14 Community for several proposed choices for details.
