Arty S7: Microblaze hello world - Memory Read Error, Microblaze instruction insert overrun

Hello, I have made an updated tutorial using Vivado 2021.1 ML

Arty S7 50 First Baremetal Software Project - Blog - FPGA - element14 Community

Can you post an image of your block design?

Hi, Sure my block design looks like this:

Thanks for sharing link to your tutorial. I will try it out as well later today. It must be something small that I missed out,...just that I haven't found what it is..YET :)

Hi, Sure my block design looks like this:

Thanks for sharing link to your tutorial. I will try it out as well later today. It must be something small that I missed out,...just that I haven't found what it is..YET :)

I see several problems in the mig_7series block

Before adding the Microblaze block your block should look like this.

It is important no to add the Miroblaze before configuring the mig_7series block. Follow the steps in the tutorial one after the other.

Hi, 

Thanks a lot for your message. After your earlier message I went through the steps in your tutorial and found a difference in how the MIG was clocked. The tutorials i followed earlier were using the 12Mhz clock feeding into a MMCM to generate the clock for MIG. I think this is what was causing the issue. Instead I removed the 12Mhz clock and the Clocking Wizard and instead fed the 100MHz clock directly to the sys_clk_i of the MIG. I also looped back the ui_addn_clk_0 of the MIG to the sys_clk_i input of the MIG. Now it's all working, infact now it's working on both Vivado 2019.1 and 2022.1.


One follow up question: The way it is now, the MIG is being fed with a 100MHz clock. What if i wanted to clock the MIG at a higher frequency? For example to increase the RAM throughput in case of an imaging application, for example? Should i add a Clocking Wizard between the 100Mhz input clock and sys_clk_i of MIG or is there a different way to go about it?

Earlier. when I was trying to fix my original problem, I tried putting a clocking wizard between the 100Mhz input clock and MIG, but I was getting some errors. I need to try this again, as I plan to try a video application with the board.

Thanks a lot for your help!

They are very interesting questions. I wish I could answer them. It is my first attempt at FPGA programming, I hope that at the end of the program I will be able to at least understand your question well. Perhaps the reference manual of the Arty S7 will help you to answer your questions. arty-s7_rm.pdf (digilent.com)

"For clocking, it is recommending that the System clock be set to “Single-ended” and connected directly to the onboard 100MHz oscillator on pin R2.

The Reference clock should be set to “no buffer” and can be connected to a 200 MHz clock generated from a clocking wizard elsewhere in the design.

It is also possible to generate the reference clock from the MIG itself by enabling “Select Additional Clocks” and generating a clock with a 5007 ps period (199.69231 MHz).

This clock will be within spec for the reference clock requirements and can be looped around back into the reference clock input of the MIG IP core.

The MIG Wizard will require the fixed pin-out of the memory signals to be entered and validated before generating the IP core."

For a first attempt at FPGA programming, you are doing INSANELY well! :D Much appreciate all you help. 

Cheers,
Saad

I'm trying to make a microblaze Spartan-7 design too. Like saadtiwana_int, I've used one before in a Zynq design. My goals will be humble: be able to talk to one FPGA  fabric input resource (a button) and one output (an LED).

It's not part of the Migration program. I'm going to take my time to do this, experiment a little. Maybe try to use an ARM soft core later ...