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VHDL vs. Verilog: Which one do you prefer and why?

rsjawale24

I started my FPGA journey with VHDL. Hence, I'm quite comfortable with VHDL. I tried learning Verilog, but it seems redundant to me as I already knew one HDL, so I gave up on learning Verilog.

However, while pursuing my master's, I saw that Verilog had become the most popular HDL and was being taught in my university and demanded in the industry.

I also find that many of the participants in the Spartan_Migration challenge are using Verilog.

Which HDL do you prefer and why? Have you tried learning VDHL or Verilog while you already knew one of them?

I like VHDL because it appears more structured and it was the first HDL I learned during my engineering days.

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  • What I have seen so far is that American and Asian companies with their affiliated Universities prefer Verilog.  European Businesses and Universities prefer VHDL.  

    Being a graybeard who learned software development and electronics long before FPGAs were accessible to hobbyists, I find the difference comparable to C/C++ and PASCAL(commercial dialects, not UCSD PASCAL).  They both do the same stuff and have very similar capabilities.  PASCAL is verbose and has fairly picky rules about what goes where, when declaring variables and structures.  C is very terse and is not as picky about the order things are declared in.

    I see the same thing with Verilog vs VHDL they achieve the same things by differing means, and they have very different histories and use cases that caused them to be invented and evolve to their current forms. I tried to learn VHDL first because it seemed easier to understand.  I found that my experience with C/C++ made me switch to Verilog as it has syntax and structure more compatible with my mental wiring.

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  • What I have seen so far is that American and Asian companies with their affiliated Universities prefer Verilog.  European Businesses and Universities prefer VHDL.  

    Being a graybeard who learned software development and electronics long before FPGAs were accessible to hobbyists, I find the difference comparable to C/C++ and PASCAL(commercial dialects, not UCSD PASCAL).  They both do the same stuff and have very similar capabilities.  PASCAL is verbose and has fairly picky rules about what goes where, when declaring variables and structures.  C is very terse and is not as picky about the order things are declared in.

    I see the same thing with Verilog vs VHDL they achieve the same things by differing means, and they have very different histories and use cases that caused them to be invented and evolve to their current forms. I tried to learn VHDL first because it seemed easier to understand.  I found that my experience with C/C++ made me switch to Verilog as it has syntax and structure more compatible with my mental wiring.

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