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VHDL vs. Verilog: Which one do you prefer and why?

rsjawale24

I started my FPGA journey with VHDL. Hence, I'm quite comfortable with VHDL. I tried learning Verilog, but it seems redundant to me as I already knew one HDL, so I gave up on learning Verilog.

However, while pursuing my master's, I saw that Verilog had become the most popular HDL and was being taught in my university and demanded in the industry.

I also find that many of the participants in the Spartan_Migration challenge are using Verilog.

Which HDL do you prefer and why? Have you tried learning VDHL or Verilog while you already knew one of them?

I like VHDL because it appears more structured and it was the first HDL I learned during my engineering days.

  • I think part of it could be just personal taste and what was taught. At uni, the lecturer taught VHDL so that's all I've tried too. 

    Also, VHDL looks reasonably different to a programming language, which could be a helpful reminder that you're not coding when it comes to FPGAs, and rather describing hardware, so I can see why a lecturer would select it.

    I happen to have one or two Verilog books just so that I can take a peek at them if I need to, but perhaps four VHDL books. I think I will struggle to learn one HDL rather than two, simply because it's not a career thing for me, so there's only finite time I can spend on just one HDL.

  • What I have seen so far is that American and Asian companies with their affiliated Universities prefer Verilog.  European Businesses and Universities prefer VHDL.  

    Being a graybeard who learned software development and electronics long before FPGAs were accessible to hobbyists, I find the difference comparable to C/C++ and PASCAL(commercial dialects, not UCSD PASCAL).  They both do the same stuff and have very similar capabilities.  PASCAL is verbose and has fairly picky rules about what goes where, when declaring variables and structures.  C is very terse and is not as picky about the order things are declared in.

    I see the same thing with Verilog vs VHDL they achieve the same things by differing means, and they have very different histories and use cases that caused them to be invented and evolve to their current forms. I tried to learn VHDL first because it seemed easier to understand.  I found that my experience with C/C++ made me switch to Verilog as it has syntax and structure more compatible with my mental wiring.

  • I much prefer VHDL, partly because I like the more precise syntax and rules, and partly becaise it's what I learned first.

    The main development tool I use (Aldec HDL) will support VHDL or Verilog.

    I'm finding that support from the more recent FPGA vendors is more Verilog focussed so I'm trying to force myself to be happy with both.

    MK

  • I learned VHDL in the early 90's in college for ASIC design. After I have dedicated to high-level software development, mainly JAVA, and I have not dealt with HDL again until now. Instead of trying to remember what I learned about VHDL I have thrown myself into learning SystemVerilog.

    I bought this book last month 

    FPGA Prototyping by SystemVerilog Examples: Xilinx MicroBlaze MCS SoC Edition | Wiley

    and it is giving me a lot of confidence with HDL.

  • I far prefer Verilog, mostly because it's more concise.  There's no way my Verilog code could fit in my binders if it were VHDL.  I'd have to get a larger office :-)

    Verilog is loosely based on C, so you have concise C notations.  I'm one of those who likes "if-then-else" expressions of the form "a? b: c".  I know some people hate that notation.  Chacun a son goût.

    VHDL is based on Ada.  I never got into Ada.  Some people love to type.  Chacun a son goût.

    My favorite commercial HDL was Altera HDL (AHDL).  You just described the hardware you wanted and "Bob's your uncle".  The problem with Verilog and VHDL (from my experience, now a few years out of date) is that you have to imagine the hardware you want, and then follow the correct template to cajole the FPGA compiler into synthesizing the correct hardware.  Verilog and VHDL were originally conceived for simulation.  Synthesis was added later, as an afterthought.  It shows.

    JMO/YMMV

  • in reply to johnbeetem

    Hey, I have an uncle called Bob too. Wink

    +1 for AHDL, I just loved the syntax. As you said, very descriptive. I only got to use it in University. 

    In real life, I only speak VHDL (the language of choice for everything defense). Also because all the companies only used Xilinx and Lattice and I could never convert any to Altera. I also use the legacy company names exclusively, because I believe the original companies, who started all the goodness shall not be forgotten. 

     = W.

  • I asked myself this same question few years ago. I will straight away jump to what I concluded.

    If you are learning for work, then you need to see what's the more popular design language in your company/region. As someone mentioned before, different regions have different preferences, and for work you'll mostly need to follow that.

    If it's not for work, then you can look at some simple modules written with both languages and compare. You might prefer one style over another. I personally chose Verilog because it's more concise and keywords are more C-like, which is what I am more comfortable with. I don't write a lot of HDL for work, though. In my city I have a lot of friends working in Intel, and from what I see, most of them are using verilog and System-verilog. 

    Good luck!