I am trying to load a image directly to the DDR SDRAM on the Art S7 board. I have converted the jpg image into a txt file containing the integer RGB values for each pixel in separate lines. The file is as shown below:
Then I created a block design in vivado for microcontroller preset with uartlite and the MIG as shown below and programmed my fpga board with this design.
Now, I am trying to open a file in Vitis and load the contents of the file byte by byte into the SDRAM memory locations with the code given below:
#include <stdio.h>
#include <stdlib.h>
#include "platform.h"
#include "xparameters.h"
#include "xil_io.h"
#include "xil_printf.h"
int main() {
char line[2];
int num = 0;
int num_rec = 0;
int i = 0;
FILE *source = fopen("C:/Users/Chinmay/Desktop/goku.txt", "r");
FILE *target = fopen("C:/Users/Chinmay/Desktop/goku_vitis.txt", "w");
if ((source == NULL) || (target == NULL)) {
xil_printf("File Failure");
exit(1);
}
init_platform();
while (fscanf(source, "%s", line) == 1) {
num = atoi(line);
Xil_Out8(XPAR_MIG7SERIES_0_BASEADDR + i, num);
i++;
}
for (long int j=0; j<4; j++) {
num_rec = Xil_In8(XPAR_MIG7SERIES_0_BASEADDR + j);
fprintf(target, "%d\n", num_rec);
}
cleanup_platform();
fclose(source);
fclose(target);
return 0;
}
Now, I doubt that my approach is wrong. In fact, I am getting some error when I try to build this code in vitis. The console output is given below:
22:44:58 **** Incremental Build of configuration Debug for project MIG1 **** make all 'Building file: ../src/main.cpp' 'Invoking: MicroBlaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -IC:/Users/Chinmay/Desktop/Verilog_Vivado/MIG1_Vitis/MIG1_wrapper/export/MIG1_wrapper/sw/MIG1_wrapper/standalone_microblaze_0/bspinclude/include -mno-xl-reorder -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v11.0 -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cpp" 'Finished building: ../src/main.cpp' ' ' 'Building target: MIG1.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -LC:/Users/Chinmay/Desktop/Verilog_Vivado/MIG1_Vitis/MIG1_wrapper/export/MIG1_wrapper/sw/MIG1_wrapper/standalone_microblaze_0/bsplib/lib -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v11.0 -mno-xl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "MIG1.elf" ./src/main.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group d:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: MIG1.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' d:/xilinx/vitis/2021.2/gnu/microblaze/nt/x86_64-oesdk-mingw32/usr/bin/microblaze-xilinx-elf/../../libexec/microblaze-xilinx-elf/gcc/microblaze-xilinx-elf/10.2.0/real-ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 88968 bytes collect2.exe: error: ld returned 1 exit status make: *** [makefile:50: MIG1.elf] Error 1 22:45:00 Build Finished (took 1s.910ms)
At the end of the 12th line, it says "region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 88968 bytes". So, my guess is that when I try to open the file, it first gets loaded into the BRAM which has less capacity than the file itself. Well, I might be wrong because when I tried to load a small 1KB file, it showed the same error.
I am stuck here. Is there any way through which I can load my file directly into the SDRAM? The size of my file is around 8MBs.
Actually I am trying to implement image processing on FPGA. I need to load an image on the board, then I will make a image processing IP in vitis HLS and use it in my design.
