Hi,
I am attempting to make an SDR receiver using an Artix-7 FPGA reading multiple ADCs and sending the raw 16 bit samples over PCIe.
I'm a strong c/c++ programmer, and have extensive hardware knowledge. But I have no FPGA programming experience.
I have installed the Vivado suite to a linux box, along with the Cable drivers. I have an Alinx AX7103 development board, along with all the sample code they provide. Vivado claims to include a PCIe IP core. I'm guessing the other blocks I need to build include a 122.88MHz clock for the ADCs, sample buffers, read calls attached to a kernel driver, INTerrupts on buffer available and ???
All of the FFT, FIR, etc. programming is done on the main computer using Cuda, keeping the FPGA relatively simple. I already have a proof of concept running on an ANAN-200D SDR which has had its FPGA lobotomized to do nothing but send samples over the 1Gb Ethernet interface. But the 1Gb channel limits me to 1/2 an ADC sample rate, so not acceptable.
The first task I need to tackle is figuring out how to hookup the included JTAG device and configure Vivado to see it and the Artix-7 behind it...
Any and all suggestions/comments/warnings welcome!
tia,
Steve