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FPGA
Forum Simple FPGA/PCIe based SDR (Software Defined Radio)
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Related

Simple FPGA/PCIe based SDR (Software Defined Radio)

ad0es
ad0es over 2 years ago

Hi,

I am attempting to make an SDR receiver using an Artix-7 FPGA reading multiple ADCs and sending the raw 16 bit samples over PCIe.

I'm a strong c/c++ programmer, and have extensive hardware knowledge. But I have no FPGA programming experience.

I have installed the Vivado suite to a linux box, along with the Cable drivers. I have an Alinx AX7103 development board, along with all the sample code they provide. Vivado claims to include a PCIe IP core. I'm guessing the other blocks I need to build include a 122.88MHz clock for the ADCs, sample buffers, read calls attached to a kernel driver, INTerrupts on buffer available and ???

All of the FFT, FIR, etc. programming is done on the main computer using Cuda, keeping the FPGA relatively simple. I already have a proof of concept running on an ANAN-200D SDR which has had its FPGA lobotomized to do nothing but send samples over the 1Gb Ethernet interface. But the 1Gb channel limits me to 1/2 an ADC sample rate, so not acceptable.

The first task I need to tackle is figuring out how to hookup the included JTAG device and configure Vivado to see it and the Artix-7 behind it...

Any and all suggestions/comments/warnings welcome!

tia,

Steve

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Top Replies

  • flyingbean
    flyingbean over 2 years ago +4
    You plan looked quite practical since you already moved FFT/FIR out off Artix 7 FPGA because the limited number of DSP slices might be a bottleneck for SDR applications. Please use latest Vitis tool from…
  • flyingbean
    flyingbean over 2 years ago in reply to ad0es +3
    Short answer for JTAG debugging: JTAG need internal RAM on FPGA to keep the snapshot of data. If the implementation is short of the LUT/RAM on FPGA, you might not get enough data for your trouble-shooting…
  • flyingbean
    flyingbean over 2 years ago in reply to ad0es +2
    Hi Steve: Please read this TRD on Artix 7 from Xilinx : https://docs.xilinx.com/v/u/1.0-English/ug964-ac701-trd-ug, ug964, Artix®-7 AC701 Base Targeted Reference Design (TRD) demonstrates, which should…
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  • dougw
    dougw over 2 years ago

    It sounds like a great project. I hope you blog about it here.

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  • ad0es
    ad0es over 2 years ago in reply to dougw
    dougw said:
    It sounds like a great project. I hope you blog about it here.

    Making good progress, for me at least!

    The board comes with 32 demo programs.  It is loaded with 01_demo, a rotating LED display of the 4 status LEDs. This demo (01) comes with a complete set of screenshots and instructions for doing synthesis, implementation, downloading a .bit file and programming a .bin file.  It is for 2019.1 on windoz10, while I am using 2022.2 on Ubuntu 22,10. So there were a few screens that differed and took some noodling to get around. I changed the LED cycle time causing a distinct difference to confirm I had made  changes. I then was able to burn the .bin file to the board.

    After documenting what I did and setting up a SVN project I amj going to jump 29_demo: PCIe Speed Test Experiment. It claims:

    The Xilinx xc7a100tfgg484-2 FPGA integrates a PCIe hard core that can be configured as X1, X2, and
    x4 for high-speed serial data communication at different rates.In the PCIe routine on the AX7103
    development board, the FPGA-side program is designed using XILINX PCIe Core, which is configured as
    x4 for PCIe communication

    Does this mean that all of the PCIe implementation (except the Transaction Layer) is already in this particular part?

    It comes with a windoz10 driver, but nothing linux that I can find ... so I have some code to write there.Unamused

    Steve AD0ES

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  • ad0es
    ad0es over 2 years ago in reply to dougw
    dougw said:
    It sounds like a great project. I hope you blog about it here.

    Making good progress, for me at least!

    The board comes with 32 demo programs.  It is loaded with 01_demo, a rotating LED display of the 4 status LEDs. This demo (01) comes with a complete set of screenshots and instructions for doing synthesis, implementation, downloading a .bit file and programming a .bin file.  It is for 2019.1 on windoz10, while I am using 2022.2 on Ubuntu 22,10. So there were a few screens that differed and took some noodling to get around. I changed the LED cycle time causing a distinct difference to confirm I had made  changes. I then was able to burn the .bin file to the board.

    After documenting what I did and setting up a SVN project I amj going to jump 29_demo: PCIe Speed Test Experiment. It claims:

    The Xilinx xc7a100tfgg484-2 FPGA integrates a PCIe hard core that can be configured as X1, X2, and
    x4 for high-speed serial data communication at different rates.In the PCIe routine on the AX7103
    development board, the FPGA-side program is designed using XILINX PCIe Core, which is configured as
    x4 for PCIe communication

    Does this mean that all of the PCIe implementation (except the Transaction Layer) is already in this particular part?

    It comes with a windoz10 driver, but nothing linux that I can find ... so I have some code to write there.Unamused

    Steve AD0ES

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