element14 Community
element14 Community
    Register Log In
  • Site
  • Search
  • Log In Register
  • About Us
  • Community Hub
    Community Hub
    • What's New on element14
    • Feedback and Support
    • Benefits of Membership
    • Personal Blogs
    • Members Area
    • Achievement Levels
  • Learn
    Learn
    • Ask an Expert
    • eBooks
    • element14 presents
    • Learning Center
    • Tech Spotlight
    • STEM Academy
    • Webinars, Training and Events
    • Learning Groups
  • Technologies
    Technologies
    • 3D Printing
    • FPGA
    • Industrial Automation
    • Internet of Things
    • Power & Energy
    • Sensors
    • Technology Groups
  • Challenges & Projects
    Challenges & Projects
    • Design Challenges
    • element14 presents Projects
    • Project14
    • Arduino Projects
    • Raspberry Pi Projects
    • Project Groups
  • Products
    Products
    • Arduino
    • Avnet Boards Community
    • Dev Tools
    • Manufacturers
    • Multicomp Pro
    • Product Groups
    • Raspberry Pi
    • RoadTests & Reviews
  • Store
    Store
    • Visit Your Store
    • Choose another store...
      • Europe
      •  Austria (German)
      •  Belgium (Dutch, French)
      •  Bulgaria (Bulgarian)
      •  Czech Republic (Czech)
      •  Denmark (Danish)
      •  Estonia (Estonian)
      •  Finland (Finnish)
      •  France (French)
      •  Germany (German)
      •  Hungary (Hungarian)
      •  Ireland
      •  Israel
      •  Italy (Italian)
      •  Latvia (Latvian)
      •  
      •  Lithuania (Lithuanian)
      •  Netherlands (Dutch)
      •  Norway (Norwegian)
      •  Poland (Polish)
      •  Portugal (Portuguese)
      •  Romania (Romanian)
      •  Russia (Russian)
      •  Slovakia (Slovak)
      •  Slovenia (Slovenian)
      •  Spain (Spanish)
      •  Sweden (Swedish)
      •  Switzerland(German, French)
      •  Turkey (Turkish)
      •  United Kingdom
      • Asia Pacific
      •  Australia
      •  China
      •  Hong Kong
      •  India
      •  Korea (Korean)
      •  Malaysia
      •  New Zealand
      •  Philippines
      •  Singapore
      •  Taiwan
      •  Thailand (Thai)
      • Americas
      •  Brazil (Portuguese)
      •  Canada
      •  Mexico (Spanish)
      •  United States
      Can't find the country/region you're looking for? Visit our export site or find a local distributor.
  • Translate
  • Profile
  • Settings
FPGA
  • Technologies
  • More
FPGA
Forum Trying to generate a modern kernel dts for avnet-uz7ev-cc board.
  • Blog
  • Forum
  • Documents
  • Quiz
  • Events
  • Polls
  • Files
  • Members
  • Mentions
  • Sub-Groups
  • Tags
  • More
  • Cancel
  • New
Join FPGA to participate - click to join for free!
Actions
  • Share
  • More
  • Cancel
Forum Thread Details
  • State Not Answered
  • Replies 7 replies
  • Subscribers 548 subscribers
  • Views 1516 views
  • Users 0 members are here
Related

Trying to generate a modern kernel dts for avnet-uz7ev-cc board.

brianmckee
brianmckee over 2 years ago

I'm using kernel 6.4.2 and the Xilinx source code appears to work for Xilinx boards, based on the presence of the dts files.

I have created avnet-uz7ev-evcc.dts and have been slowly bringing features on line by studying documentation, schematics and other dts files.

I have USB, i2c, Ethernet, and SATA working.

I'm working on DisplayPort at the moment. DisplayPort works when I boot the 2022.1 example image provided by avnet.

With my kernel, these are the only two error messages I'm getting:

[    8.294252] zynqmp-dpsub fd4a0000.display: DP output port not connected
[    8.294281] zynqmp-dpsub: probe of fd4a0000.display failed with error -22

I checked the source code and this appears to be a device tree issue.

I'm not entirely sure what is going on, but I have a question about setting the phy for DP.

On the 7ev card carrier board, the display port has only one lane. This creates issues with my monitor, but I have found a work around.

According to the main line kernel: xlnx,zynqmp-dpsub.yaml:

phys:
description: PHYs for the DP data lanes
minItems: 1
maxItems: 2
phy-names:
minItems: 1
items:
- const: dp-phy0
- const: dp-phy1

The example is:

phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;

According to psgtr documentation:
properties:
  "#phy-cells":
    const: 4
    description: |
      The cells contain the following arguments.

      - description: The GTR lane
        minimum: 0
        maximum: 3
      - description: The PHY type
        enum:
          - PHY_TYPE_DP
          - PHY_TYPE_PCIE
          - PHY_TYPE_SATA
          - PHY_TYPE_SGMII
          - PHY_TYPE_USB3
      - description: The PHY instance
        minimum: 0
        maximum: 1 # for DP, SATA or USB
        maximum: 3 # for PCIE or SGMII
      - description: The reference clock number
        minimum: 0
        maximum: 3

I think I need to set the phys to this:

       phy-names = "dp-phy0";
       phys = <&psgtr 3 PHY_TYPE_DP 1 3>;

But that, and many other combinations, doesn't work.

I'm not sure what the PHY instance is supposed to be.

I have tried 0, 1 and 3 but, I'm not sure I tried all combinations as I wasn't methodical.

I'm not seven sure this is the issue because SATA and USB work without having to set PHYS.

If anyone can offer help, I'd really appreciate it.

  • Sign in to reply
  • Cancel

Top Replies

  • flyingbean
    flyingbean over 2 years ago +1
    yes, it is device tree issue. You might need to define &psgtr clock for DP at system-user.dsti. I might not be right for your case. However, I found that DP &psgtr need some device tree setup at system…
  • flyingbean
    0 flyingbean over 2 years ago

    yes, it is device tree issue. You might need to define &psgtr clock for DP at system-user.dsti. I might not be right for your case. However, I found that DP &psgtr  need some device tree setup at system-user.dsti after Petalinux 2021. If you cannot find solution until end of this month,  I might have time to help you with that. I might have time for the trouble-shooting after the coming week.

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • brianmckee
    0 brianmckee over 2 years ago in reply to flyingbean

    Are you using peta-linux? I'm using the mainline kernel.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • flyingbean
    0 flyingbean over 2 years ago in reply to brianmckee

    Yes. I am using Petalinux. I don't know how to use mainline kernel under Yocto flow.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • brianmckee
    0 brianmckee over 2 years ago in reply to flyingbean

    If I can get the mainline kernel working, then getting a yocto flow working will be way easier. However, generating the device tree for the PL is probably way more complicated that way. But that's my plan.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • flyingbean
    0 flyingbean over 2 years ago in reply to brianmckee

    Since the platform is Xilinx, I would like to use Petalinux to generate device tree files for the targeted Xilinx FPGA, which can be used as a reference for your mainline kernel development.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • brianmckee
    0 brianmckee over 2 years ago in reply to flyingbean

    The Xilinx kernel is very outdated and uses a very different set of device tree descriptors and, as I understand, there's even a difference in the drivers.

    I don't want to be stuck on kernel 5.15 as there are many changes since then.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • flyingbean
    0 flyingbean over 2 years ago in reply to brianmckee

    How about Kernel 6.1? It would be  a good lift for your trouble-shooting.

    image

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
element14 Community

element14 is the first online community specifically for engineers. Connect with your peers and get expert answers to your questions.

  • Members
  • Learn
  • Technologies
  • Challenges & Projects
  • Products
  • Store
  • About Us
  • Feedback & Support
  • FAQs
  • Terms of Use
  • Privacy Policy
  • Legal and Copyright Notices
  • Sitemap
  • Cookies

An Avnet Company © 2025 Premier Farnell Limited. All Rights Reserved.

Premier Farnell Ltd, registered in England and Wales (no 00876412), registered office: Farnell House, Forge Lane, Leeds LS12 2NE.

ICP 备案号 10220084.

Follow element14

  • X
  • Facebook
  • linkedin
  • YouTube