Actions
Forum Thread Details
  • State Not Answered
  • Replies 3 replies
  • Subscribers 493 subscribers
  • Views 582 views
  • Users 0 members are here
Related

Suggestions for designing with ZYNQ MPSoC UltraScale+ ZCU104: Using PS side DDR4 memory for storing trained weights and biases of Convolutional Neural Network(CNN) for implementation of CNN inference in real-time.

BinitKP

I have trained weights and biases from a CNN network for different layers. I have converted those data into fixed point 16-bit binary format and saved them as .txt files for different convolutional layers. Since the data files are too large to accommodate them into BRAM (On-chip memory), I need to use external PS side DDR4 memory to store those.

However, I don't understand how I can store those data in DDR4 memory for simulation purposes as the Verilog function of $readmemb() says out of memory in the Vivado while loading a single file as I think it is taking the BRAM only; which is too small in capacity.

So, please guide me on how to approach the simulation and then real-time inference operation after making the equivalent CNN using Verilog HDL coding, whether my approach is correct or if I need to approach it another way.

Attached are the file organization and sample contents for reference.

imageimageimage

Parents
  • 0

    I believe you can mimic the behavior of the data transfer engine from DDR to your internal module inside your testbench! Am I right?

    You can read the .txt file in your testbench, and handle the hand shake required for your data transfer in your simulation bench. I am assuming you are using AXI_DMA, reading the data in AXI_MM world and your module wrapper is AXI_S compatible which makes it easier. 

Reply
  • 0

    I believe you can mimic the behavior of the data transfer engine from DDR to your internal module inside your testbench! Am I right?

    You can read the .txt file in your testbench, and handle the hand shake required for your data transfer in your simulation bench. I am assuming you are using AXI_DMA, reading the data in AXI_MM world and your module wrapper is AXI_S compatible which makes it easier. 

Children
No Data