Hello everyone,
We recently purchased four ZCU208 boards and are in the process of extending an HDL Coder–based design to support eight-channel IQ data capture. While the single-DMA reference design works fine, we’ve run into several roadblocks trying to scale this to a dual-DMA setup. I’d like to outline the issues here and see if anyone in the community has experience or workarounds.
Background
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Board: ZCU208
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Flow: MATLAB/Simulink HDL Coder (R2023b / R2024a)
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Starting point: Avnet RFSoC Explorer Toolbox reference design (single DMA, validated on hardware)
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Goal: Add a second AXI DMA to stream 8-channel complex data at higher throughput
Challenges Encountered
1. Reference Design Integration
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The Avnet Explorer Toolbox single-DMA plugin integrates fine.
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Attempting to extend to dual DMA requires modifying:
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plugin_rd_dualdma.m
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system.tcl
(to instantiate/connect the second DMA)
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We confirmed that the older
ReferenceDesignPlugin
class approach is unsupported in R2023a/b. -
Factory-based plugin (
hdlcoder.ReferenceDesign
) works in R2024a, but integration remains unstable. -
MathWorks support confirmed that dual-DMA examples are not provided in their documentation (e.g., Chapter 35), and that ZCU208 is not officially supported.
2. FIL Workflow Limitations
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Using FIL snapshot mode:
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Theoretical capture: ~31k IQ samples for 8 channels (given 1 MB buffer, 32 bytes/sample).
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Practical result: Only ~2k samples for 4 channels before buffer limits hit.
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This makes FIL unsuitable for high-throughput testing, meaning dual-DMA streaming is mandatory for our use case.
3. Toolchain & Device Tree
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Even with a functional dual-DMA block design in Vivado, HDL Coder integration requires manual PetaLinux device tree updates.
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Without this step, Linux drivers won’t recognize the second DMA.
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At present, HDL Coder alone does not provide a clean, supported way to integrate this.
Questions for the Community
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Has anyone successfully integrated dual AXI DMA with ZCU208 using Avnet’s reference design as a base?
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If so, was the workflow MATLAB-centric, or did it require deeper Vivado/Device Tree customization?
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Are there any known workarounds or examples (Element14 or otherwise) for extending the Avnet Explorer Toolbox to multi-DMA?
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Given the FIL capture bottleneck, is there a better recommended flow for validating 8-channel high-rate IQ streaming on ZCU208?
Closing
We’d greatly value insights from others who may have solved similar integration challenges. Since we’ve already invested in multiple ZCU208 boards, we want to avoid reinventing the wheel if community knowledge exists.
Thanks in advance for any guidance, links, or even partial solutions that can help move this forward.