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ZCU208 RFSoC Explorer Toolbox Dual AXI DMA Integration & FIL Workflow Limitations with HDL Coder

100asut01

Hello everyone,

We recently purchased four ZCU208 boards and are in the process of extending an HDL Coder–based design to support eight-channel IQ data capture. While the single-DMA reference design works fine, we’ve run into several roadblocks trying to scale this to a dual-DMA setup. I’d like to outline the issues here and see if anyone in the community has experience or workarounds.

Background

  • Board: ZCU208

  • Flow: MATLAB/Simulink HDL Coder (R2023b / R2024a)

  • Starting point: Avnet RFSoC Explorer Toolbox reference design (single DMA, validated on hardware)

  • Goal: Add a second AXI DMA to stream 8-channel complex data at higher throughput

Challenges Encountered

1. Reference Design Integration

  • The Avnet Explorer Toolbox single-DMA plugin integrates fine.

  • Attempting to extend to dual DMA requires modifying:

    • plugin_rd_dualdma.m

    • system.tcl (to instantiate/connect the second DMA)

  • We confirmed that the older ReferenceDesignPlugin class approach is unsupported in R2023a/b.

  • Factory-based plugin (hdlcoder.ReferenceDesign) works in R2024a, but integration remains unstable.

  • MathWorks support confirmed that dual-DMA examples are not provided in their documentation (e.g., Chapter 35), and that ZCU208 is not officially supported.

2. FIL Workflow Limitations

  • Using FIL snapshot mode:

    • Theoretical capture: ~31k IQ samples for 8 channels (given 1 MB buffer, 32 bytes/sample).

    • Practical result: Only ~2k samples for 4 channels before buffer limits hit.

  • This makes FIL unsuitable for high-throughput testing, meaning dual-DMA streaming is mandatory for our use case.

3. Toolchain & Device Tree

  • Even with a functional dual-DMA block design in Vivado, HDL Coder integration requires manual PetaLinux device tree updates.

  • Without this step, Linux drivers won’t recognize the second DMA.

  • At present, HDL Coder alone does not provide a clean, supported way to integrate this.

Questions for the Community

  1. Has anyone successfully integrated dual AXI DMA with ZCU208 using Avnet’s reference design as a base?

  2. If so, was the workflow MATLAB-centric, or did it require deeper Vivado/Device Tree customization?

  3. Are there any known workarounds or examples (Element14 or otherwise) for extending the Avnet Explorer Toolbox to multi-DMA?

  4. Given the FIL capture bottleneck, is there a better recommended flow for validating 8-channel high-rate IQ streaming on ZCU208?

Closing

We’d greatly value insights from others who may have solved similar integration challenges. Since we’ve already invested in multiple ZCU208 boards, we want to avoid reinventing the wheel if community knowledge exists.

Thanks in advance for any guidance, links, or even partial solutions that can help move this forward.

  • 0

    Hello.Good to see you're getting some use out of the ZCU208 HDLC Support Package. The functionality your asking for is not limited by our support package, rather it's directly related to what HDL Coder is able to do in the version of MATLAB you're using. Our examples are ported directly from the examples included in MathWorks HDL Coder support for the ZCU216. You may want to try opening a case with MathWorks with your request above to understand what they currently support.

    Thanks, /Matt

  • 0 in reply to mbrown

    Matt — thanks for the follow-up.

    To put this to rest:

    • My requirement is dual-AXI DMA for 8-channel IQ snapshot on ZCU208 using MATLAB R2023a + Vivado 2020.2 + PetaLinux 2022.2.

    • MathWorks has confirmed ZCU208 is not supported in R2023a for the HDL Coder/Verifier flow I’m using; the first mention of ZCU208 support is in much newer releases and doesn’t address this dual-DMA use case.

    • Avnet RFSoC Explorer Toolbox is not supported by MathWorks, and your ZCU208 content (ported from ZCU216) doesn’t provide a dual-DMA reference design or a documented path to get there under R2023a.

    Given the above, this has become a finger-pointing exercise between toolchains rather than a solution path. We’re closing out ZCU208 under HDL Coder and moving forward with alternatives (ZCU111 under native MathWorks support and industry-standard flows for ZCU208).

    Constructive suggestion: please update the Toolbox documentation to clearly state (1) the exact MATLAB/Vivado/PetaLinux combinations validated for ZCU208, (2) that dual-DMA is not provided, and (3) the lack of MathWorks support for this Toolbox—so others don’t spend weeks rediscovering these limits.

    No further action needed on this thread from my side. Thanks.

  • 0 in reply to 100asut01

    Hi there. Sorry for your frustration on this. I was hoping to point you on a vector of help instead of blame. Thanks for your suggestion on improving the docs. Best of luck with your project!

  • 0 in reply to 100asut01

    In case others arrive here, I'll leave behind clips from our online documentation for ZCU208 HDL Coder Support Package.

    image

    Although MathWorks HDLC FIL allows hybrid versions of PetaLinux and Vivado, we decided to keep ours aligned on 2020.2 until MathWorks harmonize PetaLinux and Vivado support beyond 2020.2.

    RFSoC Explorer supports ZCU208 HDLC flows in R2023a (and older). You'll need to go to the download page and click the "Version History" tab to find versions that support MATLAB releases older than the two most recent.