How do FPGA development/evaluation boards create from scratch?

you will need to understand the EDA package you are going to use, including multi-layer design, and you will have to be able to fully understand the design and lay-out guidelines for the IC.

Thanks Jan,

Would you mind tell me more about the details?

For example:

1. Which EDA tools do people usually use?

2. Do people manually calculate the resistors or capacitors volume or the EDA could calculate it automatically?

3. etc.

You know, there are a lot of different boards with different specs in the market. I can not believe that all of the designers know everything about electronics and PBC design. So I want to know, as a digital electronic guy (with knowledge about VLSI), how can I become one of them?

Dave Vandenbout from XESS, who makes the XuLA FPGA board that I'm using, has published a video on PCB design for FPGA on KiCAD:

https://www.youtube.com/watch?v=EHtcOrdl9Xw

I don't know what software others use.

Here are some general comments, not specifically for the Xilinx Zynq.

You have to be very careful with layout design with a high-performance FPGA.  Usually the vendor supplies an application note called "Design Guidelines" or "Layout Guidelines" or "PCB Guidelines".  These are critically important.  Here are some of the typical considerations:

1.  Every wire and via in a PCB is an inductor with resistance.  The thinner the wire (or smaller the via), the higher the inductance and resistance.  The longer the wire the higher the inductance and resistance.

2.  Attach as many power and ground connections as possible, and make those connections as short as possible to the power/ground planes.  A lot of high-performance FPGAs are BGAs, which means that most of the connections are through tiny vias, each of which has inductance.  Since there are lots of vias, the power and ground planes under your FPGA may end up with so many holes that they resemble swiss cheese.  This adds inductance to your power and ground signals.  Buried vias help.

3.  You need bypass capacitors for your power pins.  These need to be "as close as possible" to the power and ground pins, since all connections to them are inductors.  Fitting in bypass caps is very challenging for a high-performance FPGA in a small package with dense pinout.

Look up "ground bounce".  This is a phenomenon that occurs when multiple signals change voltage simultaneously.  These changes need to source or sink a bunch of current, which comes from your bypass capacitors and exits through your ground connections.  Inductors don't allow fast change in current, so if the power/ground connections have too much inductance you get nasty noise pulses on signals that aren't changing.  FPGA vendors provide guidance on this as well: look for "simultaneous switching".  One thing that helps a lot is to slow down your output signals by configuring them for lower current or slower slew rate.  It also helps to use lower-voltage signals: 1.8V instead of 3.3V, for example.

4.  If you have PLLs they'll need their own "analog VDD" with some RC or LC filtering.  This should be in the Design Guidelines.

5.  If you have differential signals like HDMI, SATA, PCIe or Gigabit Ethernet, follow the design guidelines rigorously.  Any mismatch between differential signals will create nasty problems and you won't even be able to see what's going wrong unless you have an expensive 'scope with expensive differential probes.

Fun, isn't it?  And I'm not even an analog designer or PCB layout expert.  Successful high-performance FPGA design usually requires a team: digital expert, analog expert, and PCB layout expert.

Usually your best approach is to copy the development/eval board directly.  Smart vendors explicitly allow you (and encourage you) to do this, and even provide PCB layouts for your PCB layout expert to copy.  A smart vendor figures that if you copy a known working design, your product will be more likely to be successful sooner (which is the only way they'll sell you large quantities of ICs) and you won't need as much help from application engineers.

Woooow! That was huge! Thanks for the info, very helpful.

1. What EDAs does the team need to do the design?

2. Which member of the team is responsible for circuit calculates (e.g. capacitors' volumes, resistors' values and etc.)? Is it also mentioned in the document?

3. If the EDAs can simulate the design, how is it possible to end up with a big fail (I'm not considering manufacturing defects)?

That was an awesome video. I also found another one.

Thanks a lot for sharing.

These days I mostly do the FPGA design part of a product.  It's been over 10 years since I did any PC board design myself, though I still review PCB schematics.  When I was doing PC board designs, I used ORCAD which was decent back then.  I think our layout guy used PADS PCB.  But that was 10 years ago and software can evolve or devolve a lot in 10 years, so go with recommendations of recent software.

Caps and resistors are really easy for the digital side.  You generally use lots of 0.1 uF ceramic caps for high-speed bypass, and add a few 10 uF multi-layer caps for bulk capacitance.  Use at least twice the voltage spec you need.  Resistors are usually 4.7K for pull-ups and 33 Ohm for series termination at the source of transmission lines.  If you use tiny SMT parts be careful that you don't exceed the power rating.  Capacitor values are usually in the design guidelines.  Go ahead and copy R/C values from the development board.

We didn't do simulation of either PC boards or FPGAs.  If you carefully follow the design guidelines you probably won't need to simulate boards, and it's often impossible to get simulation models for parts anyway.  For FPGAs, as long as you leave enough spare pins and spare logic cells you should be able to program around errors.  I did a little FPGA simulation when I was first getting started with them just to make sure I wasn't completely off base.  I was horrified to find that simulation wasn't any better than 20 years earlier.  Then the board came back and it promptly failed due to phenomena that simulation couldn't model.  So that was that.

A lot of people prefer to do simulation, figuring that it's easier to catch and correct errors at the simulation level than when you have actual hardware.  Chacun a son goût.  I find preparing stimulus and expected response "test benches" to be incredibly tedious and I'd much rather spend that time debugging the real hardware.  I do lots of FPGA synthesis to make sure the design runs fast enough and fits in the FPGA.  This was mostly with Xilinx Synthesis as part of ISE WebPack.  I've never used Vivado.

One thing I found very useful was to verify that the netlist used for PCB layout agreed with the schematic.  This was a fairly tedious manual process, but I usually found at least one error, e.g., a net that should have had one name but ended up with different names on different schematic pages, so they didn't get connected on the PCB layout.  With fine-pitch devices, and especially BGAs, this can be a killer so it was worth doing.  I usually had to write a quick program to convert the PCB software's netlist into something more readable.

Mostly I agree with John's suggestions - I'm still involved in hardware design and design small FPGAs into things often. I'm also part of projects working with larger FPGAs but I don't do the pcb design but am involved with hardware design and review.

But I'll add a few things.

1) You can't expect to just jump in and make these things work - to design in a reasonable sized FPGA with DDRAM and other high speed interfaces you need a design team with at least 25 years of combined experience of this kind of work. (5 years at least of PCB, digital hardware, power supply, FPGA system architecture, mixed signal project management)

2) When you copy a reference design, then copy EXACTLY, or else have a very good reason to deviate.

3) Design for debug - if you need to link BGA or very fine pitch packages then think about how you will monitor the signals on them - there is a reason that you see zero ohm resistors in signal lines and it isn't that the designer forgot that there was on chip termination.

4) Read the design material for the FPGA family, several thousand pages of relevant stuff your team must understand to use Zynq Ultrascale+

5) Start small - Zynq Ultrascale+ is out of your range - just buy a ZCU104 if you want to play with the big chip, or if you really want to design a board start with Lattice XP2 or Altera MAX10 (come in TQFP packages and have on chip config memory).

MK

Thank you all for the replies. I learned a lot and it's now much more clear for me.

Guys one of the things that I really like about this community is the way people answer any types of questions. People really try to help the questioner no matter how silly the question is (despite of some other forums!). It really attracts me to ask more questions. I'm a newbie in hardware world and there are many things I've learned as theories, but I want to know what's happening in the real world (which mostly cannot be found in any textbooks).

I hope one day I back to this topic with my own experience and talk about my experiences for the next generation of hardware designers just like other people did today .

Thanks a lot.

Mohammad

Great, Mohammad!

... these days you can start to learn for an acceptable price. There are EDAs that are free, or free for personal use. And the price to let a PCB company make and ship small boards has dropped under 10$.

I've used that market situation to practice PCB design, by starting to create very simple small boards.