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PL-based processors and PS-based processors communication

manili

Hello everyone,

 

Would someone help me find the answer to the following questions:

I have a ZCU104 board (Zynq Ultrascale+) and I want to program the PL with multiple tiny processing cores. As far as I know, the 2GB DDR4 SDRAM is connecting to the PS part of the chip, so I cannot connect my tiny processing cores to the memory directly.

1. How can I share the memory among all processing cores inside both PS (4 x ARM Cortex-A53) and PL (for example MicroBlaze or RISC-V)?

2. If it is not possible then how can these processing units talk to each other?

Thanks a lot.

P.S. Please take a look at page 24:

https://www.xilinx.com/support/documentation/boards_and_kits/zcu104/ug1267-zcu104-eval-bd.pdf

  • Hi Mohammad,

     

    I'm not an expert (complete beginner actually - day #1) so this could be completely wrong:  wouldn't DMA via AMBA AXI interfaces be used for this?

  • in reply to shabaz

    Dear ,

     

    I think this is the correct answer, but I'm not sure about it just like you. However, the problem shows itself when we are going to design a many-core system. Now how to handle it? Should we create an arbiter which talks to the DMA or is it better/possible to create an L2 cache as a middle-man to talk to the DDR4 RAM?

  • in reply to manili

    Not sure I'm afraid : (

    It may be a comp-sci type of question though.. maybe authors like Hennessy & Patterson may have written about the ways to implement this, e.g. maybe even using a packet switching capability. I've never implemented it myself. Hopefully others can chime in, it's beyond my knowledge area : (

  • in reply to manili

    Hi Mohammad,

     

    There are many different ways to design memory architectures for multi-cores systems, and ultimately it depends on the goal set for your system. It is quite a vast area of study, but here you can find some presentation slides that go over some common architectures used. I'm afraid I'm not an expert either on multi-core memory design, but at least the slide should give you some pointers on where to dig for more in-depth information.

     

    Fabio

     

    P.S: for DDR4 access from PL, there was a similar question posted for the ZCU102 dev board on the Xilinx forum. I know the two boards are quite different, yet I think the information might still be useful.

  • There is almost no point at all in programming the FPGA part of a Zynq with lots of little processors each with access to the system DDRAM - why - because the access to the DDRAM will make a bottleneck rendering the mutiple cores useless.

     

    What you could do is give each core access to its own block RAM in the FPGA fabric. The cores need to be able to talk to each other.

     

    As Fabio has pointed out  there are many lifetimes of published work on this subject.

     

    It would be possible to help you more if you put the question into some kind of context - what are you trying to do (end goal of your project).

     

    Why do you want lots of tiny cores ?

     

    MK

  • Hi all,

     

    Thank you very much for the replies.

    First of all please let me share with you the link I've found for my main question:

    https://youtu.be/cDc9B2zAPz4

    In these 4 series of session 7, Mohammad S. Sadri explains how to connect an IP core (for example graphics accelerator), to the external memory (in my case DDR4 SDRAM) and PS part (in my case 4 x ARM Cortex-A53), using the AXI4-bus standard.

    Please bear with me that I mislead the main topic with my second question. So as a result, I finally found the answer to my main question with your help and the video series. Now should I continue the second question (about implementing the many-core design on the board) here or I must create a new topic?

     

    Manili