FlaviaLB60-01.zip contains data files for the FlaviaLB60 implementation of the Free Logic Array, described in Flavia: the Free Logic Array and Chapter 12 of The XXICC Anthology rev 0.1. FlaviaLB60 is for the ValentF(x) LOGI-Bone FPGA board, rev R1.0. To reduce chances of confusion, I recommend that you only install this file if you want to synthesize Flavia logic for the LOGI-Bone.
FlaviaLP60 rev 0.1 uses n-bit integers in SevenSegLB.xoe.
Unless you're using JTAG, FlaviaLB60 rev 0.1 may not work with the new LOGI-Bone-2, marked R1.5.1 on the PC board. LOGI-Bone-2 has a different I2C GPIO expander and changes its pin assignment, so programming LOGI-Bone-2 directly from BBone is slightly different. Flavia 0.1 programs LOGI-Bone by writing a bitstream to "/dev/logibone" (used by original LOGI-Bone) or to "/dev/LOGIBone" (used by LOGI-Bone-2). However, I haven't tried it since I don't have a LOGI-Bone-2.
If you've been able to get Flavia running on LOGI-Bone-2, please add comments below telling us what worked. If you're having trouble getting LOGI-Bone-2 to work, add comments and/or e-mail me and we'll figure it out.
Note: LOGI-Bone-2 changed the default FPGA configuration mode from Slave Serial to Master Serial/SPI, i.e., self-config. So when you power it on, LOGI-Bone-2 tries to read a valid bitstream from on-board serial Flash. Flavia can override it, but if there's a valid bitstream it will affect whatever you have hooked up to LOGI-Bone-2 pins.
There may be other LOGI-Bone-2 changes that affect Flavia. I don't have the new board to test things at this time.
Flavia is part of XXICC. For more information on GalaxC and XXICC, see the 'blog post XXICC (21st Century Co-design) release 0.1 and XXICC's home page xxicc.org.
This work is licensed under the Creative Commons Attribution-ShareAlike 3.0 Unported License. To view a copy of this license, visit creativecommons.org/licenses/by-sa/3.0/. No warranty is expressed or implied.
