Actions
Engagement
  • Author Author: pchan
  • Date Created: Date Created
  • Last Updated Last Updated:
  • Views 15204 views
  • Likes 20 likes
  • Comments 169 comments
Related
Recommended

FPGA Developer Quiz

profile image
sponsored by image

Quiz | Summer of FPGA: Microchip | Microchip | Resource | Summer of FPGA: Main Agenda |FPGA image

FPGA Developer Quiz

FPGA Developer Quiz
Complete our Essentials: FPGA Developer Quiz, earn 100% on the quiz and give the page a star...

Do you know enough to be an FPGA Developer? Prove it by taking our FPGA Developer Quiz, with topics such as Microchip's Polarfire FPGAs.

To earn the FPGA Developer Badge, score 100% on the quiz, rate this document, and leave your feedback on the quiz as a comment.

 

       
Parents

  • Answer for question 12 is wrong. FPGAs can have (much) lower latency than Microprocessors but it's got nothing to do with operating systems.

     

    I didn't guess all the Microchip specific stuff correctly, but knowing how many IOs a particular manufacturer's FPGA contains is something you look up.

     

    Q16 is a bit misleading - some Flash based FPGAs use nonvolatile memory cells to directly set the logic, others use SRAM cells and  a built in serial flash memory to automatically programme them on power up.

    These devices are still marketed as Flash FPGAs but suffer from slower start up time and erratic startup current.

    AFAIK Microchip Flash FPGAs are the non volatile fabric type.

    The Intel/Altera MAX10 parts are examples of an SRAM based FPGA with built in config NV memory. The biggest part (10M50) can take 139ms to start up (worst case).

     

    MK

  • in reply to michaelkellett

    Hi Michael,

    Thanks for your comment!

     

    Question 12 comes from Video #2 of Microchip's FPGA video course: https://mu.microchip.com/hello-fpga/585486

    They say it's mainly due to depending on an operating system, but don't elaborate further. You're definitely right, though, there are other factors. I'll do some research and figure out how to word that better. Same for Q16...that's good info!

    Thanks!

    Dave

     

     

     

    https://mu.microchip.com/hello-fpga/585486

  • in reply to dychen

    Typically a processor would need to:

     

    read input register

    compare bits

    write output register

    loop

     

    and would need 100% of its attention on this task,

     

    or it could use interrupts:

     

    hardware interrupt on IO bit change

    stack registers (typically > 8 clocks)

    write output register

    return from interrupt

     

     

    An FPGA could use clocked and synchronised logic,

    typically taking three or 4 clock cycles to respond

     

    or asynchronous logic, taking less than 1 clock cycle to respond

     

    And the FPGA could have tens or more of such functions operating simultaneously whereas a processor can only manage one without getting slower.

     

    MK

  • in reply to michaelkellett

    Awesome thanks...this is really helpful!! I'll work on rewriting the question.

    Thanks,

    Dave

Comment Children
No Data