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What is Source Down Technology?
The power management market has become increasingly concerned with energy efficiency, power density, cost, and improved lifetimes for end applications. While advancements in Silicon technologies have pushed the envelope of key performance parameters, new package concepts offering groundbreaking benefits are scarce. With the introduction of their new Source-Down technology and the release of a whole new product family, Infineon is leading the way in defining a new industry standard footprint.
Infineon Technologies focuses on system innovation with enhancements on the component level. Their Source-Down technology was designed in an effort to improve MOSFET performance, reducing on-state resistance (RDS(on)) and offering better thermal management capability. The first wave of Infineon power MOSFETs launched in this new package is the OptiMOS TM IQE006NE2LM5. It is a low power MOSFET based on Source-Down Technology that enhances electrical and thermal performance, enabling the power density needed in modern applications. The product is suited for a range of applications such as drives, SMPSs (including server, telecom, and OR-ing), and battery management.
The Source-Down Package Explained
This Source-Down innovation simply inverts the Silicon die inside the MOSFET package. The source potential is thus connected to the lead frame instead of the drain potential. Figure 1 shows the structure of the new Source-Down technology compared to conventional Drain-Down technology. In Source-Down, the Silicon die's gate and source connection is directly established on the lead frame. A large copper clip connects the drain’s electrical connection from the top of the die. The drain, source, and gate's electrical connection continue to be at the exact location, making a drop-in replacement extremely easy.
Figure 1: The internal construction of a PQFN 3.3x3.3 mm Drain-Down power MOSFET (left) and the internal construction of a PQFN 3.3x3.3 mm Source-Down power MOSFET (right)
Image Source: Infineon
These new footprints provide the benefits of improved RDS(on) and power density, a highly optimized layout, reduced thermal resistance, and also new thermal management capabilities. We will now discuss each of these benefits further.
Improved RDS(on) and Power Density: Inverting the die removes some construction limitations which have been a consistent problem for standard drain-down devices. The Source-Down approach enables the use of larger dies and reduces RDS(on) by 30%, and lower RDS(on) is directly linked to the reduction of I2R losses in the application and leads to greater power densities.
Optimal Layout: Another key benefit of the Source-Down Technology is the effective layout option, enabling high power density and high system efficiency. Source-Down comes in two different footprint versions: Source-Down Standard-Gate and Source-Down Center-Gate. For the Center-Gate version, the gate-pin is moved to the center, supporting easy parallel configuration of multiple MOSFETs. In this version, with its larger drain-to-source creepage distance (0.75 mm), it is possible to connect the gates of multiple devices on a single PCB layer. Figure 2 shows the difference in the footprints of the PQFN 3.3x3.3 mm OptiMOS MOSFET family. Drain, Source, and Gate electrical connections continue to be at the exact location, making a drop-in replacement easy.
New Thermal Management Capabilities: With the Source-Down concept, the thermal pad of the MOSFET is on the ground potential, thus enabling the use of thermal vias (to allow heat transfer) right underneath the device. This also improves the RthJC of this product family, from 1.8 K/W down to 1.4 K/W, leading to a more than 20 percent improvement.
Figure 2: Comparison of a standard Drain-Down device with the new Source-Down footprints Image Source: Infineon
OptiMOS 25V Low-voltage Power MOSFET
The Source-Down OptiMOS power MOSFET comes in a PQFN 3.3x3.3mm package size, making it easy to use in the same PCB routing as the Drain-Down IQE006NE2LM5 solution. The on-state resistance (RDS(on)) of the device is reduced to a significant factor of 0.65mΩ with Source-Down technology. It also adds a significant shrinkage of the form factor. The same performance as a 5x6mm SuperSO8 is now achievable in a PQFN 3.3x3.3mm (Figure 3) for more efficient PCB real estate use. The new Source-Down technology in the IQE006NE2LM5 enables overall higher system efficiency and power density in the end application. Table 1 summarizes the key performance parameters. The critical features of the IQE006NE2LM5 low power MOSFET are as follows:
Table 1: Key Performance Parameters
• Major reduction in RDS(on) by up to 30% compared to current technology
• Improved RthJC over current PQFN package technology
• Standard-Gate and Center-Gate footprints available
• New optimized layout possibilities
The IQE006NE2LM5 Source-Down package technology enhances electrical and thermal performance, enabling the power density needed in modern datacenter applications. To compare the performance benefits, two versions of an 8:1 HSC (hybrid switched-capacitor) are considered, using the contemporary standard Drain-Down device (BSZ011NE2LS5I) on one board and the new Source-Down device (IQE006NE2LM5) on the other. The HSC DC-DC converter is a new intermediate bus converter (IBC) solution for a 48 V power-delivery architecture, providing high efficiency and high power density for data centers and AI servers. The HSC (Figure 3a) is a creation of six MOSFETs bifurcated into two legs, connected through two flying capacitors and a magnetic device called a multi-tapped autotransformer. Figure 3b compares the thermal performance of the devices. The standard package shows a hot-spot that is eliminated with the use of the new Source-Down package. The MOSFET surface temperature is significantly improved, showing a 9°C difference compared to the Drain-Down device. Figure 3c illustrates the efficiency comparison, including auxiliary losses. The system's higher efficiency featuring the new source-down device leads to a significant jump in power density.
|Figure 3a||Figure 3b||Figure 3c|
Figure 3a: HSC converter topology. 3b: The thermal behavior of the HSC at 450 W from 48 V input with BSZ011NE2LS5I and IQE006NE2LM5. 3c: The HSC converter efficiency.
Image Source: Infineon
For more information: about Infineon power management products, click here for more information.
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