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Documents Programmable Electronic Load - ADC and DAC BoosterPack test
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  • Author Author: Jan Cumps
  • Date Created: 24 Nov 2017 11:12 AM Date Created
  • Last Updated Last Updated: 2 Dec 2017 10:04 AM
  • Views 4978 views
  • Likes 7 likes
  • Comments 35 comments
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Recommended

Programmable Electronic Load - ADC and DAC BoosterPack test

WIP

 

This blog documents the characteristics of the DAC/ADC BoosterPack of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

We have the same DAC/ADC BoosterPacks so we can compare the measurements of each ADC and DAC channel. Check the main document for anything related to hardware and firmware.image

 

Test Setup

 

Peter has created a GUI that we can use to shoot SCPI commands. We can control the DACs and read the ADCs.

Measurements are performed with and without the power driver BoosterPack installed. We'll use 5V to power the DACs and ADCs in both situations.

 

image P1 and P2 on the bottom of the DAC/ADC BoosterPack have to be open. Else you'll inject 5V onto the LaunchPad 3V3 rail and you'll damage components.

 

It's not critical if you switch on the power supply before or after you connect the LaunchPad to your computer. The circuits are isolated.

All measurements use P3.10 as GND reference and P3.1 as reference voltage.

 

image

 

Setup without the power driver BoosterPack:

Mount the DAC/ADC BoosterPack on the LaunchPad.

Use a +5V power supply. It should be a decent one, current is approximately 5 mA.

Connect image with DAC/ADC BoosterPack P4.2  and image with P4.1.

 

Setup with the power driver BoosterPack:

Mount the DAC/ADC BoosterPack on the LaunchPad and the Power Driver BoosterPack on top of that.

On the Power Driver BoosterPack, bridge pins P2.4, P2.5 and P2.6 to tie both opamp inputs of opamp 3D to ground.

Use a +12V power supply. It should be a decent one, current is approximately 50 mA.

Connect image  with Power Driver BoosterPack P1.1 image  and with P1.2.

 

image

 

Measurements

 

In the table, the first column shows what we're measuring, the second column the SCPI command to execute with Peter's GUI.

The next columns are the measurements for Peter, Jon or Jan with and without the Power Driver BoosterPack.

The last column is for comments. We can indicate odds, errors, learnings.

 

JonPeterJan
Data PointSCPIWithoutWithWithoutWithWithoutWithMeasurement method
SupplyN/A4.989 V11.88 VDMM
DAC/ADC V+N/A4.989 V5.035 VDMM
VREFN/A2.046 V2.046 VDMM
ADC A GNDDEVE:ADC1?2SCPI output
ADC A VREFDEVE:ADC1?10918SCPI output
ADC ADEVE:ADC1?1138SCPI output
ADC B GNDDEVE:ADC2?12SCPI output
ADC B VREFDEVE:ADC2?10920SCPI output
ADC BDEVE:ADC2?1
SCPI output
ADC C GNDDEVE:ADC3?22SCPI output
ADC C VREFDEVE:ADC3?1092010919SCPI output
ADC CDEVE:ADC3?26868SCPI output
ADC D GNDDEVE:ADC4?83SCPI output
ADC D VREFDEVE:ADC4?1091910919SCPI output
DAC A 0DEVE:DAC1 00.000 V0.001 VDMM
DAC A maxDEVE:DAC1 655352.040 V2.040 VDMM
DAC B 0DEVE:DAC2 00.005 V0.005 VDMM
DAC B maxDEVE:DAC2 655352.046 V2.046 VDMM
DAC C 0DEVE:DAC3 00.000 V0.000 VDMM
DAC C maxDEVE:DAC3 655352.039 V V2.039 VDMM
DAC D 0DEVE:DAC4 00.000 V0.000 VDMM
DAC D maxDEVE:DAC4 655352.039 V2.039 VDMM

 

 

To resolve

With the power driver installed, ADC C and D act strange (probably also A and B, but I didn't inject a voltage in them because they are connected to opamp pins).

In particular strange for ADC D, because that one isn't routed. Strange.

I will try to decrease the frequency of the sample speed and the i²c speed to see if it's related to that ...

 

Follow up: the cause is that OPAMP 3C injects -0.8V into ADC A. All measurements are off when that happens. As soon as I force ADC A positive (by tying it to ground or a positive voltage) all measurements are correct.

 

image

 

We have a separate document to analyse the summing node at zero.

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Top Comments

  • shabaz
    shabaz over 8 years ago +3
    Hi Jan, I was wondering, what are the expected values, is it reading a value representing 1.602V when it should read a value representing 2.048V? I'm wondering if it could be due to conversion time (i…
  • Jan Cumps
    Jan Cumps over 8 years ago in reply to shabaz +3
    yes, Shabaz, I have a controlled value of 2.040 V. Once I mount my additional driver board (self-designed so many things can be wrong ) the ADC says it’s 1.6 V. I checked signals with my scope to see if…
  • jc2048
    jc2048 over 5 years ago in reply to Andrew J +3
    Andrew J , have you read the blog I did when building Jan and Peter's load? That has some material on the low end of the DAC. Long story short, I adapted the analogue stuff after the DAC so the output…
Parents
  • Jan Cumps
    Jan Cumps over 8 years ago

    For some reason it's working now. I'm not comfortable because I don't know the reason.

    I've removed and plugged in everything - but I've done that umphteen times before.

     

    With the board:

    (I didn't drive ADC C because that's a diret output from an opamp without any resistor between opamp and ADC so I don't want to fidle with that)

     

    DEVE:ADC1 = -0.006

    DEVE:ADC2 = 0.000187500

    DEVE:ADC3 = -0.00468750

    DEVE:ADC4 = -0.00431250

     

     

    DEVE:ADC1 = 2.03662

    DEVE:ADC2 = 0

    DEVE:ADC3 = 2.03888

    DEVE:ADC4 = 2.03944

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    For some yet to understand reason: if I tie ADC A to ground then all others work fine. odd ...

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    owkey. There's -0.799V on that pin and the ADC doesn't like that at all. Once I push that ADC pin to 0 or higher, all channels work fine.

    So we can now look at the opamp that's feeding ADC A.

    image

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  • jc2048
    jc2048 over 8 years ago in reply to Jan Cumps

    Do you have the current sense resistor attached?

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to jc2048

    no. Nothing from the off-board power components. I haven't purchased them yet. So the inputs for the sense opamp are floating -> output can be anything -> may be the cause for the woes ...

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to jc2048

    There's good news. If I tie both inputs of the current sampling opamp 3C (the one that feeds back into the summing node) to ground, the negative voltage disappears.

    I now get a fairly stable reading on all four ADCs.

    It's very likely that this turns out to be a non-issue.

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to jc2048

    There's good news. If I tie both inputs of the current sampling opamp 3C (the one that feeds back into the summing node) to ground, the negative voltage disappears.

    I now get a fairly stable reading on all four ADCs.

    It's very likely that this turns out to be a non-issue.

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  • Robert Peter Oakes
    Robert Peter Oakes over 8 years ago in reply to Jan Cumps

    Good, I was hoping it was not my design image, once I saw you mention the - voltage it seemed to indicate a floating current sense input, glad it was something simple

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Jan Cumps

    Some test points:

    The 5.036 V on the ADC3 (measured with a DMM) is sampled as 5.0364

     

    With all inputs of opamp C tied to ground and the DAC A set to 0 V, the voltage at the summing node (measured with a DMM between R3 and R4) is 0.018 V

    This results in a voltage going out of opamp B into ADC A of -0.212V (also measured with a DMM on the pin of ADC A). The ADC reads -0.2130 V.

     

    I've been running the device for many hours now. Things aren't drifting

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  • Jan Cumps
    Jan Cumps over 8 years ago in reply to Robert Peter Oakes

    Robert Peter Oakes, I've made a document to investigate the summing node of the design: Programmable Electronic Load - Analyse the Summing Node Zero Point

    Let's check what drives this away from 0V and if we can compensate that ...

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  • Robert Peter Oakes
    Robert Peter Oakes over 8 years ago in reply to Jan Cumps

    As soon as I get the parts and build mine up, I will be in testing things out

     

    from a summing junction perspective, think of it as simply a pair of resistors where one end is the input and the other is the feedback, the middle should always return to zero, pretty simple when thought of that way

     

    of course we have added op amps etc in the feedback loops etc just to make it more interesting image

     

     

     

    Peter

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