Programmable Electronic Load - ADC and DAC BoosterPack test

Thanks for reminding me though Jon, it's still useful to know.  From the post I added below, you can see that I have to find a way to dial out a 20mV (probably less on a PCB) offset error and I will want to do that on the control board, not leave it to a downstream consumer.

I did pick on the Microchip part because it was good value for money and I've never used one before to know what to look for.  Right now, I have a lot more appreciation for what the gain/offset/INL/DNL specs in the datasheet mean. 

Test data results.  I've only measured the first 30 input codes in the graph but I will do more.  Having added the DC/DC Isolated converter to power Side A of the i2c and digital isolators (the Arduino input side) it has impacted the DAC output quite a lot, even though that is powered from a REF5040 (4.096) supply which I have measured at 4.096V.  That is used as the reference point for generating the DAC output.  My first conclusion is that noise is getting on to Side B ground from the DC/DC convertor although that is powered from a regulated 12V supply.

I need to have a look at that but this is all on a breadboard right now so I'm only looking at (a) making sure my circuit works; and (b) working out an approach for tuning the DAC and ADC readings so that I can do it for real once I have a PCB.

Nonetheless, I'm showing here an Ideal, Actual and Compensated DAC output with the derivation for the compensation calculation.  It's looking a lot more linear than I first thought and it has the same look as the graphs Jan and Jon produced!  It's also worth mentioning that the readings fluctuated by +/- 500uV around the value captured (e.g. at 0x000 input, I was reading anything from 0.0203 to 0.01998) but what I logged was the most stable - i.e. the reading that stayed steady the longest:

EDIT: I've just noticed that the DAC input code runs from 1 to 31 - I should have edited these labels to read 0 to 30 so please read it on that basis.

I don't intend to post more updates here unless Jan requests it as this is only related to the extent it's about DAC output.

OK. Thought I'd point them out just in case.

I'm not an analogue designer, so can't really guide you much as to the good ways to do this sort of thing. I got involved in the load to give Jan a little bit of help with sorting out some of the op amp stuff [which I know in theory, even if not so well in practice]. I then got interested in it from a control systems point of view [it's a PID controller - I was intending to have a go at 'tuning' it better, but haven't gotten around to it].

I ought to pick it up again and see if I can do a bit more with it. I stalled at the 'building it into a box with a dirty great heatsink on top' stage which I need to do to run it at any real power. As it is at the moment, it's all rather fragile, with separate boards lashed together and difficult to work with.

The Microchip part I used with the FPGA was 'good value for money' and would be perfectly suitable for many uses, but obviously has its limitations.

The TI device brings out the -ve end of the resistor chain, so it doesn't have to be connected to zero volts. I would think if you lifted it up a bit with a false earth, the output op amp doesn't then need to get right to the rail and you then avoid at least that limitation, though at the expense of much more external complexity. Whether that's the 'right' way to do it, I've got no idea.

Yes, I read through the whole set of material, more than once, over the last year - I found it really interesting although I'd be a liar if I said I understood half of it. 

I'd originally started following Peter's series on power supply but that sort of faded away and instead led into the work that Jan carried on with the DC load.  I hadn't made the connection between the offset of the DAC I'm using (a Microchip one as it happens) and what you and Jan were/are seeing here.  The datasheet implies that the offset measured with an input code of 0x000 applies across the range and can be removed by software.  How, it doesn't say, and I'm not wholly convinced because it's not possible to feed a -ve input code to it which would be needed to drop 7mV down to 0.  That then leaves the gain which can be measured and applied at different points in the output and factored out.  Overall, that's the equation that Jan is using:  ActualInput = (Input * GainCompensation) - Offset Compensation.  That still leaves INL and DNL errors.  The compensation values on that formula I think will change through the range of outputs because I don't think they are linear - it's hard to tell of course, because the INL and DNL errors skew things.  Also, I haven't had time yet to do any comprehensive measurements to get a better feel for it.

Overall accuracy requirements will impact as well I guess: if a 1V output should genuinely be 1.000000V then that's going to be a lot more work than allowing for 0.999nnnV to 1.001nnnV.  I haven't made that decision yet as I'm still happily designing and trying out my own version.  In any case, from what I've investigated so far, it would seem that DACs will have errors in their outputs and that will have to be dealt with as part of downstream design as appropriate for need.  Something that you have done by the sounds of it.

Andrew J , have you read the blog I did when building Jan and Peter's load?  That has some material on the low end of the DAC. Long story short, I adapted the analogue stuff after the DAC so the output didn't need to get to zero.

Programmable Load Build

There's also something along similar lines for a Microchip DAC in the following blog. I didn't do anything about the low end there because I didn't need to, but it illustrates what the internal op amp buffering the DAC output is doing and might be of interest:

FPGA: Making Waves

Tthat would be great - I’m sure I could learn a lot from you.  What I’ll do is write up what I’m doing and ping it over.  I’m using a 4Duino - spare one from when building my power supply - as the mcu.  I’m at the point of having the circuit breadboarded and a number of test sketches to drive it.  The dc/dc isolator has arrived so I will be trying that out tomorrow as it’s the biggest issue I have right now.

I was just thinking about a control board at the moment, but it is a similar approach

Yes, this is not load specific.

I tried with just two values (multiplier and additive), but it wasn't accurate enough (so why I thought a lookup table in EEPROM would be needed) and I had read that an OpAmp approach may help but I haven't investigated that at all.  The problem is the offset and the gain are not linear across the output range so a formulaic approach won't be enough.  Can't ignore the impact of INL and DNL on the output.

I experienced that too, but I don't want to spend time on this if I don't get feedback. I got no animo on this subject here on e14. I didn't have a burning need so I stopped where the blog stopped.

If you're going down this path, I'd like to join and share/compare experiences. I have the hardware and firmware to try out some approaches with you.

I tried with just two values (multiplier and additive), but it wasn't accurate enough (so why I thought a lookup table in EEPROM would be needed) and I had read that an OpAmp approach may help but I haven't investigated that at all.  The problem is the offset and the gain are not linear across the output range so a formulaic approach won't be enough.  Can't ignore the impact of INL and DNL on the output.  I have made a start on the test you mention, but only just so it will take a little while to get some results.  Once I have a set of results I can see if there's something within the data that allows me to derive a formula from it but that's highly unlikely - the datasheet states that the gain error only really kicks in at the higher range so it may be possible to do something simpler below that range. 

I've not built/designed a DC load for this, I was just thinking about a control board at the moment, but it is a similar approach to the one you and Peter took.  I am mainly doing it to have a play with a DAC and ADC and the problems that arise.  I guess there are only so many ways you can hook a DAC and ADC up, but I found what you did very interesting.

Can you run a test that shows the output of the DAC vs the input value, for a range

• starting from DAC input == 0
• to a point where the output is showing a linear rise, then some additional poins?

In my case, the DAC did not react for a number of input values (until the offset was reached),

then started to work linear once that point was reached.

I's a rough read, because it's a series of comments and tests, but here we're trying to address the offset: https://www.element14.com/community/docs/DOC-88254/l/programmable-electronic-load-analyse-the-summing-node-zero-point#co…

I made a PCB to test it. It fixed the DAC offset but never fixed the issues of the eLoad at the near-0 point...