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Documents Programmable Electronic Load - Analyse the Summing Node Zero Point
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  • Author Author: Jan Cumps
  • Date Created: 1 Dec 2017 4:08 PM Date Created
  • Last Updated Last Updated: 15 May 2020 3:38 PM
  • Views 8699 views
  • Likes 8 likes
  • Comments 107 comments
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that Robert Peter Oakes, jc2048 and Jan Cumps are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

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Top Comments

  • jc2048
    jc2048 over 7 years ago in reply to Robert Peter Oakes +4
    As you say, changing the op-amp is one possibility. There are bipolar op-amps with much lower bias currents, but an alternative nowadays is a precision CMOS op-amp (you'd have to check whether other characteristics…
  • Robert Peter Oakes
    Robert Peter Oakes over 7 years ago +3
    To hopefully simplify things a little We have this, Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1 Lower right op amp measures the volts across…
  • jc2048
    jc2048 over 7 years ago in reply to Jan Cumps +3
    Love the advertisement for "John's excellent probes". It's like one those things from the old days of American TV where the presenter would suddenly turn, look very earnestly at the camera, and start reading…
  • Jan Cumps
    Jan Cumps over 5 years ago in reply to jc2048

    ADC A raw values. The output of the current sense OpAmp as measured by our circuit, then sent through a -1 gain amp

    image

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  • jc2048
    jc2048 over 5 years ago

    What's the lefthand axis on that last plot? mA? uA?

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  • Jan Cumps
    Jan Cumps over 5 years ago in reply to Jan Cumps

    Jan Cumps  wrote:

     

    Pushing the offset higher doesn't solve the issue. It just pushes it uphill.

    In this graph, I set DAC B, that creates the offset correction, to 300.

     

    image

    Behaviour is the same, a steep jump from nothing to > 2 mA, but at a higher starting point of DAC A.

     

     

    1840,00051850,00251860,00251870,00261880,00281890,00291900,003

     

    (are we fighting against the diodes at the backside of the integrator?)

    The conclusion may be premature, but the cause for the bump seems to be the offset in the current sense opamp.

    When working that offset in the U3C away to under 200 µV, I get nicer behaviour when the regulation circuit starts.

    image

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  • jc2048
    jc2048 over 6 years ago

    Jan Cumps

     

    I've done a bit more with mine. Rather than add another op-amp, I offset the 0V that the summing node gets compared to. See the last section of my build blog for more details

     

    Programmable Load Build

     

    That gives me this at the low end

    image

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Robert Peter Oakes

    Robert Peter Oakes,

     

    - I had an issue with the DACs of the DAC/ADC board. They can have a positive offset, and that can cause the firmware not to be able to manage the lowest region. That’s fixed with a substracting opmamp and using a free DAC channel to offset that offset.

     

    - there’s a more fundamental issue that the control circuit jumps at the region between no load and a slight load. It seems to be tolerance=based, because that sudden jump is from 0 to 1.3 mA on my instrument, and slightly below 1 mA on jc2048‘s board. It’s not related to DACs or firmware. That’s the jump that I show in my last comment here. After that jump, the instrument behaves linear.

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  • Robert Peter Oakes
    Robert Peter Oakes over 6 years ago

    Hi Jan and all

     

    I see this is still providing a great deal of fun for one and all, I need to get cought up and see if I can help.

     

    anyone provide a quick summary of were you are at and what the issue is

    Thanks

    Peter

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to Jan Cumps

    It still shows that jump when the circuit starts to load

    image

     

    edit: detail at the knee

     

    imageimage

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    It works now - with proper resistor values. I'll try to find a DAC1 DAC2 combination that gives a good start near 0..

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  • Jan Cumps
    Jan Cumps over 6 years ago in reply to jc2048

    too late for now, everything is built up again. I can always do it at a later time.

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  • jc2048
    jc2048 over 6 years ago in reply to Jan Cumps

    I found it: all resistors on my bodge board are 100 Ohm instead of 100K.

    So they are. It was staring us in the face in that photograph you posted - '101' marked on the tops.

     

    Personally, I'd change them all for 10k (including the two summing resistors) to get the currents up an order of magnitude, but that's probably just me being fussy.

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