Programmable Electronic Load - Analyse the Summing Node Zero Point

This is unfair on Peter. It's his design yet you're having all the fun of sorting out the prototype.

But if you're intent on doing this anyway...

"On my board I measure a potential of -0.212V at the left side of R33"

You need to measure the output of U3B too - it might be lower. The ADC will have some form of ESD protection and that might clamp the voltage. Only way to know is to measure both ends of R33 and see if they are different.

Then you need to measure the output of U3C. You have two amplifiers in series and you need to know how much of a contribution each is making to whatever offset you measure at the output of U3B. That will give you some useful clues as to what is going on.

(As Peter points out the meter input resistance will affect the readings, so start with measuring the outputs of the amplifiers because they are the lowest impedance points in the circuit and your meter has the least effect on them - the output impedance will be under a hundred ohms.)

jc2048  wrote:

 

"On my board I measure a potential of -0.212V at the left side of R33"

You need to measure the output of U3B too - it might be lower. The ADC will have some form of ESD protection and that might clamp the voltage. Only way to know is to measure both ends of R33 and see if they are different.

 

Then you need to measure the output of U3C. You have two amplifiers in series and you need to know how much of a contribution each is making to whatever offset you measure at the output of U3B. That will give you some useful clues as to what is going on.

jc2048  wrote:

 

"On my board I measure a potential of -0.212V at the left side of R33"

You need to measure the output of U3B too - it might be lower. The ADC will have some form of ESD protection and that might clamp the voltage. Only way to know is to measure both ends of R33 and see if they are different.

 

Then you need to measure the output of U3C. You have two amplifiers in series and you need to know how much of a contribution each is making to whatever offset you measure at the output of U3B. That will give you some useful clues as to what is going on.

Love the advertisement for "John's excellent probes". It's like one those things from the old days of American TV where the presenter would suddenly turn, look very earnestly at the camera, and start reading out the advert. Perhaps we could see if John would like to sponsor this episode of Circuit Conundrums (starring Jan Cumps as The Man with the Meter).

The interesting figure is the 0.104V at the summing node. If there was only R2 and R4 in circuit, that voltage could only be 0.054V (give or take a little for the resistor tolerance). The fact that it's so high suggests that there's an additional contribution to the current through R2 from what's connected beyond the dotted line.

The second clue is U3B. The op-amp is doing a good job of keeping the virtual earth at pin 6 close to GND, yet it has to position the output at -0.212V to do it (and not the -0.108V you would expect given the 0.108V at the output of U3C).

What do they both suggest?

In case anyone's interested in why the readings look to be out, here's a quick analysis of the situation.

Jan has measured the voltages and we know the resistance values, so we can calculate the currents in each resistor for the two pairs. Like this...

The additional current into the node where the resistors join is then the difference between the two. The only place that current can come from is the op-amp, so Jan is doing an experiment to measure the input bias current of the input pins of the actual op-amp that he has on the board - the bias current for this particular op-amp flows out of the pin (shown with a negative sign on the datasheet).

Here's what the datasheet says

so he's not  too far out, their typical figure is 0.8uA and he is measuring around 1uA. Well inside their maximum value (at 25C) of 2uA. (I've ignored any meter loading in all this.)

So a couple of possibilities

Change the op-amp or reduce the 100K s to reduce the effect of the op-amp node, this would increase the risk of a fault condition blowing the op-amp but would fix the error, relatively of course, by going to say a pair of 20K we would improve things by 5*

Thoughts?

As you say, changing the op-amp is one possibility. There are bipolar op-amps with much lower bias currents, but an alternative nowadays is a precision CMOS op-amp (you'd have to check whether other characteristics were good enough).

Lowering the resistor values would be good anyway, but there's a limit to how far you can go and it still leaves quite an error. The measured value is way out and though you could try and compensate in software it's messy because it will vary from unit to unit.

A third option, that a textbook would give you, is to balance the input resistances. It's something that Jan could try quickly with what he's already built, if he wanted to.

For the inverting amplifer U3B, lift the non-inverting pin and connect a 50k resistor from the pin to ground. (If you don't have a 50k 1% resistor, use two of the 100k ones in parallel.)  That gets you this

the output of U3B should now be much closer to the gain of -1 and with 0.108V going in should read within a millivolt or two of -0.108V. At least that's what theory says. Try it and see.

To understand why it works, look at the line above the one I highlighted on the datsheet (offset current). That's saying that, although the bias current is fairly high, the difference in the bias current of the two inputs is quite small (no more than one part in a hundred - less than 1%). That comes about because, although the bias current is the base drive to a transistor and is a bit variable  (it will vary from batch to batch), the transistors on a particular chip match very well in their characteristics (because they're all fabbed together). That matching can be made use of.

For this part, the bias current is out of the input pin (it's the base current of a PNP transistor). When it flows through whatever resistance is connected to the pin it generates a voltage. If the resistance seen by both inputs is the same, then those voltages will be the same (we don't know precisely what the voltage will be, because the bias current varies quite a lot, but we do know that both inputs will see a very similar additional voltage because the currents match well). Since the two inputs are difference inputs, the two voltages will then pretty much cancel out as part of the normal action of the op-amp.

After Jan had done that (and assuming that it worked), he could then move on to the differential amplifier (U3C). To achieve the same effect there he merely needs to install the 680k to ground. Then we can see how close it brings things overall to the kind of accuracy you want. I suspect you'll want to move to a more up-to-date precision part (particularly if Jan is hoping to get anything close to the accuracy implied by working 16 bits), but let's see (and it's an interesting experiment to do, anyway).

I'll try the 3rd option next weekend. I don't specifically need the precision but it's an interesting exercise. I think I'll pass on using a higher precision opamp for now. Time to move on to the high piwer part, then get operational firmware.

jc2048  wrote:

...

 

A third option, that a textbook would give you, is to balance the input resistances. It's something that Jan could try quickly with what he's already built, if he wanted to.

 

For the inverting amplifer U3B, lift the non-inverting pin and connect a 50k resistor from the pin to ground. (If you don't have a 50k 1% resistor, use two of the 100k ones in parallel.)  That gets you this

 

the output of U3B should now be much closer to the gain of -1 and with 0.108V going in should read within a millivolt or two of -0.108V. At least that's what theory says. Try it and see.

 

To understand why it works, look at the line above the one I highlighted on the datsheet (offset current). That's saying that, although the bias current is fairly high, the difference in the bias current of the two inputs is quite small (no more than one part in a hundred - less than 1%). That comes about because, although the bias current is the base drive to a transistor and is a bit variable  (it will vary from batch to batch), the transistors on a particular chip match very well in their characteristics (because they're all fabbed together). That matching can be made use of.

 

For this part, the bias current is out of the input pin (it's the base current of a PNP transistor). When it flows through whatever resistance is connected to the pin it generates a voltage. If the resistance seen by both inputs is the same, then those voltages will be the same (we don't know precisely what the voltage will be, because the bias current varies quite a lot, but we do know that both inputs will see a very similar additional voltage because the currents match well). Since the two inputs are difference inputs, the two voltages will then pretty much cancel out as part of the normal action of the op-amp.

 

...

I have added the 50K from non-inverting input to ground of U3B.

The voltage at that input is 0.051 V.

On the output, it's - 0.106 V.

jc2048  wrote:

 

...

 

After Jan had done that (and assuming that it worked), he could then move on to the differential amplifier (U3C). To achieve the same effect there he merely needs to install the 680k to ground. Then we can see how close it brings things overall to the kind of accuracy you want. I suspect you'll want to move to a more up-to-date precision part (particularly if Jan is hoping to get anything close to the accuracy implied by working 16 bits), but let's see (and it's an interesting experiment to do, anyway).

With R32, 680K in place, the voltage at the entry of ADC1 is -0.005V as measured by my DMM,

The ADC measures -0.00581250 V (65506)

Does it still affect the other ADC channels (going negative by only 5mV) or is it going to be usable in normal operating conditions?

You've still got the problem with abnormal conditions - ie if someone connects the load output the wrong way round. Perhaps the way to deal with that would be to make it a 'perfect diode' circuit, though that wouldn't give you any warning that the output was connected wrongly.

5mV error is a bit better than 200mV, so it's a definite improvement (worth having for two extra resistors). But it's only 40 times better and substituting an op-amp with bias currents maybe a thousand times less would give much more benefit.

If you take a look at the datasheet above, you'll see that the voltage offset error is typ 0.5mV and may be more. Amplified by the 6.8 gain of the differential amplifier, that gives the potential for several millivolts of error at the ADC input. Saying it another way, the reduced bias current error is now around the same level as the voltage offset errors, which means, if you want to go further and try and make it even more precise, you're trying to work with (and disentangle) two error sources rather than just the one.

jc2048  wrote:

 

Does it still affect the other ADC channels (going negative by only 5mV) or is it going to be usable in normal operating conditions?

 

...

The ADC seems to behave well up to at least -250 mV, and has errors on all channels when one input is below -700 mV. I haven't checked the in-between yet to find the tipping point - and haven't investigated the datasheet for this condition.

jc2048  wrote:

 

...

 

You've still got the problem with abnormal conditions - ie if someone connects the load output the wrong way round. Perhaps the way to deal with that would be to make it a 'perfect diode' circuit, though that wouldn't give you any warning that the output was connected wrongly.

 

...

Yes, I will have to test what situations can cause negative values on ADCs in normal conditions too.

jc2048  wrote:

 

...

 

 

5mV error is a bit better than 200mV, so it's a definite improvement (worth having for two extra resistors). But it's only 40 times better and substituting an op-amp with bias currents maybe a thousand times less would give much more benefit.

 

If you take a look at the datasheet above, you'll see that the voltage offset error is typ 0.5mV and may be more. Amplified by the 6.8 gain of the differential amplifier, that gives the potential for several millivolts of error at the ADC input. Saying it another way, the reduced bias current error is now around the same level as the voltage offset errors, which means, if you want to go further and try and make it even more precise, you're trying to work with (and disentangle) two error sources rather than just the one.

An exercise for the future or for someone who wants to improve the design - and certainly an interesting one.

The bad connections is or should be a one time issue during build, it should not occur after that

The issue comes up once the built in protection diodes start to conduct, aka about 250mV ish