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  • Author Author: Jan Cumps
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Programmable Electronic Load - Analyse the Summing Node Zero Point

This blog documents investigates the feedback node of the electronic load that , and are designing.

It's an important spot in the load's design. It measures the set point and the feedback from the output.

When the output is driven to 0, it should be on a potential as close as possible to 0 V.

On the first prototype it's -0.2 V. Not so much off, but the negative value  influences our ADC measurements.

This document checks how we can get this node to 0 V.

image

 

Because this document is evolving, some comments below may be out of sync with the content. That's because the content is adapted based on the conversation.

The measurements taken here are based on the original design, without R32 in place and U3B + tied to ground.

The current sense side of R7 is connected to ground, and a variable negative voltage from 0 V down is applied to the current sense side of R8 to simulate current being sensed.

 

The circuit isn't complex. The set point is driven by a DAC. It's set to 0 for this test.

The second input to this node is OpAmp 3C. It has both inputs tied to ground so should theoretically have 0 V at the output.

On my board I measure a potential of -0.212V at the left side of R33.

I hope to get this closer to 0 V to ease the ADC a bit - its performance degrades with negative voltage at its inputs.

Like the other blogs for the electronic load, this is a working document that will be updated with findings from anyone who wants to chime in.

 

Behaviour at 0V

 

buzy image

Parents

  • To hopefully simplify things a little

     

    We have this,

     

    Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1

    Lower right op amp measures the volts across the shunt and amplifies it tot he same range as the set point from DAC

    Lower left op-amp integrates the difference of the two (Based on value of summing junction) so if the sum is not zero then the integrator will attempt to correct it by driving the mosfet more on or off..

    image

     

     

    So simplifying the diagram we end up with this

    image

    if the measured value is equal and opposite to the set point then the sum junction will of course be zero, this relies on the two resistors being the same value, if not perfect then it can be corrected in software.

    All the silicon is to get the ranges the same and of the correct polarities for this to work, also the integrator is relied upon to make fast changes if the difference is great and small slower changes as they get close together, all pretty standard stuff

     

    What I think Jan is seeing is a none zero value at the sum when in fact it should be zero, this could be the resistors are not the same value but the SP and Actual are the same but opposite.

     

    Also consider that the meter you measure with is 10MOhm input impedance (May be less but probably this, check the meter manual)  this will have a measurable affect on the sum junction, perhaps 1% (10M in parallel with 100K), it may be better to use a high impedance meter if you have one or use the output of the integrator as you guide. (Or do the math to see what you would actually expect with 100K in series with 100K and 10M in parallel image

Comment

  • To hopefully simplify things a little

     

    We have this,

     

    Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1

    Lower right op amp measures the volts across the shunt and amplifies it tot he same range as the set point from DAC

    Lower left op-amp integrates the difference of the two (Based on value of summing junction) so if the sum is not zero then the integrator will attempt to correct it by driving the mosfet more on or off..

    image

     

     

    So simplifying the diagram we end up with this

    image

    if the measured value is equal and opposite to the set point then the sum junction will of course be zero, this relies on the two resistors being the same value, if not perfect then it can be corrected in software.

    All the silicon is to get the ranges the same and of the correct polarities for this to work, also the integrator is relied upon to make fast changes if the difference is great and small slower changes as they get close together, all pretty standard stuff

     

    What I think Jan is seeing is a none zero value at the sum when in fact it should be zero, this could be the resistors are not the same value but the SP and Actual are the same but opposite.

     

    Also consider that the meter you measure with is 10MOhm input impedance (May be less but probably this, check the meter manual)  this will have a measurable affect on the sum junction, perhaps 1% (10M in parallel with 100K), it may be better to use a high impedance meter if you have one or use the output of the integrator as you guide. (Or do the math to see what you would actually expect with 100K in series with 100K and 10M in parallel image

Children
  • in reply to Robert Peter Oakes

      wrote:

     

    To hopefully simplify things a little

     

    We have this,

     

    Upper op amp is simply to provide an inversion of the measured value back tot he ADC, hence the gain of -1

    Lower right op amp measures the volts across the shunt and amplifies it tot he same range as the set point from DAC

    Lower left op-amp integrates the difference of the two (Based on value of summing junction) so if the sum is not zero then the integrator will attempt to correct it by driving the mosfet more on or off..

    image

     

     

    So simplifying the diagram we end up with this

    image

    if the measured value is equal and opposite to the set point then the sum junction will of course be zero, this relies on the two resistors being the same value, if not perfect then it can be corrected in software.

    All the silicon is to get the ranges the same and of the correct polarities for this to work, also the integrator is relied upon to make fast changes if the difference is great and small slower changes as they get close together, all pretty standard stuff

     

    What I think Jan is seeing is a none zero value at the sum when in fact it should be zero, this could be the resistors are not the same value but the SP and Actual are the same but opposite.

     

    Also consider that the meter you measure with is 10MOhm input impedance (May be less but probably this, check the meter manual)  this will have a measurable affect on the sum junction, perhaps 1% (10M in parallel with 100K), it may be better to use a high impedance meter if you have one or use the output of the integrator as you guide. (Or do the math to see what you would actually expect with 100K in series with 100K and 10M in parallel

    , thanks for the scenario. What I am investigation is if we can avoid negative voltage at the ADC A pin. On my device it's -0.2 V and that doesn't impact the measurements of ADC channel B, C and D.

    I'd have to see how much below zero we can have before the ADC starts to error (all channels are 30% off with -0.8 V on ADC A), and then check how we can control that this situation doesn't occur.

  • in reply to Jan Cumps

    Ok. So it's sounding like the real desire is to protect the ADC rather than

    stop an op amp doing its thing. A double shotky may be the answer to

    bolster the internal diodes and to trigger before the internal ones. This

    can be had in some very small packages but would also need a resistor to

    limit the current. Though I think the op amp could handle the load without

    cooking itself. What do you think ??. This is pretty standard practice too

    I believe so I'm dissapointed I did not think of it earlier.

  • in reply to Robert Peter Oakes

    I was thinking about avoiding this particular ADC input influencing (shouting over) the other 3 ones. That would be difficult to handle in firmware.

     

    As long as we can keep the negative voltage above the range that it starts to influence ADC channel B, C and D we are good.

     

    This is not an issue of your design. It's introduced by the ADCs.

  • in reply to Jan Cumps

    As this seems to be an issue of overloading the protection diodes in the ADC, im not sure if using a different channel is the best fix, it may work but might just move the problem to something else. One other thought I just had was a diode across the feedback of the inverting amplifier, this way it will have a full gain of -1 in one direction but way less int he other limiting the output to less than 100 or 200mv, or across the inputs to the opamp, I dont have my kit yet so im just thinking in my head till it arrives image