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  • Author Author: Jan Cumps
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Programmable Electronic Load - Power Stage

This blog documents focuses on the power stage of the electronic load that , and are designing.

 

image

In this post we're laying out a PCB for the power stage - as much as possible with surface mount components. The FET is close to the one uses in the original design.

 

The BOM

 

ComponentHeader 2Header 3Header 4
P18 pin header, 2.54mm
P2 abinding post, redhirschmann 931714101hirschmann 931714101 -  SOCKET, 4MM, BLACK, PK5 , MLS
P2 bbinding post, blackhirschmann 931714100hirschmann 931714100 -  SOCKET, 4MM, BLACK, PK5 , MLS
P3 abinding post, blacktenma 2301tenma 2301 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Black
P3 bbinding post, redtenma 2302tenma 2302 - Binding Post, 36 A, 500 V, Nickel Plated Contacts, Panel Mount, Red
TH1NTC Thermistor, 10KVishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC
Q1N-Channel MosfetInfineon IRF3205SPBFInfineon IRF3205SPBF -  MOSFET Transistor, N Channel, 110 A, 55 V, 8 mohm, 10 V, 4 V
D1, D2DiodeDIODES SBR2A40P1-7DIODES SBR2A40P1-7 -  Standard Recovery Diode, PowerdiRegistered, 40 V, 2 A, Single, 500 mV, 50 A
R1100R1206 any brand
R20R05Vishay WSHP2818R0500FEBVishay WSHP2818R0500FEB -  SMD Current Sense Resistor, 0.05 ohm, 10 W, 2818 [7146 Metric], ± 1%, WSHP2818 Series
Cooler HeatsinkStartech.com FAN370PRO - Socket 7/370 CPU Cooler Heatsink and Fan

 

 

 

NTC

 

For a detailed description on the temperature protection mechanism, check Programmable Electronic Load - Temperature Protection.

 

The voltage sent to the ADC is very dependent on the NTC. I've selected a Vishay NTCS0805E3103JLTVishay NTCS0805E3103JLT -  THERMISTOR, 10K, 5%, SMD, NTC.

I'll program the key values. The behaviour is non-linear and it's easier to make a lookup table if the firmware has to be able to deal with different components.

This will require access to flash to permanently store tha values, and a SCPI function to alter the table if another component is used.

For the first version I'm going to be selfish and just program for the device that I've ordered.

image

 

PCB

 

Exposed copper

 

For good thermal relief, and to get the NTC as good termally coupled to the FET as possible,

I placed a copper pour (here on the front, I'll do the same on the back and stitch them for thermal transport with vias)

Then i drew a pour on the front mask. The area of pour will expose copper. That means that the NTC has physical contact with the copper that the FET is soldered on.

In the fine-tuning I will place that NTC closer to the FET so that I can put a tad of heat paste in between. Or I could put a tad of paste between the NTC and exposed copper ...

image

 

Attention when placing the binding posts. For the power input, RED is 1 and BLACK is 2.

For the sense input, BLACK is 1 and RED is 2.

This is the result of me labeling pin 7 and 8 of the connectors between the driver board and FET board wrong, on both boards image.

The documentation and KiCAD zips are now updated with corrected schematics.

 

I used these 2 Contextual Electronics videos to refresh how to expose copper layers and place VIA arrays:

 

Here's the top side of the completed design. I've drawn the FET in green to give perspective.

image

In red you see the copper layer, orange is where the solder mask is removed and copper exposed.

Pink are the drill holes. They are 0.9652 mm, in an array of 9 * 8, spaced 2 mm apart.

image

 

On the bottom, the copper pad (green) has the size of my heat sink + some. The removed mask (blue) has the exact size of the sink's bottom profile.

The pink lines are the mounting slots for the heat sink (see below).

image

 

Slots

 

My heat sink has brackets for mounting. I've cut out slots to allow the brackets to through the PCB and fix them on the top side.

 

image

 

I've put some exposed non-connected copper pour around the slots for strength.

The slot is drawn on the Edge.Cuts layer. I hope that the PCB fab interprets that as slots to be milled out ...

image

 

I've attached the KiCAD project, component libs and Gerbers in a single zip. Also the VIA lib that's used here as a separate file (because I share that one across projects).

Attachments:
vias.pretty.zip
eload_offboard_20171227.zip
  • in reply to Jan Cumps

    I tried 20k (because I have them) for R2 and R4.

    The gate voltage now is at -4.231 when DAC is 0V or INPUT disabled.

    It starts going up when I set the DAC to 200 (0.006V) , gets instable around 320 (up to the point that putting my voltmeter over it is rather impacting) and flips over to a gate voltage of +0.594 at DAC set to 330 (0.009V)

    It never goes over that 0.594 gate voltage for the rest of the DAC range (max 2.040V).

     

    I'll bodge a set of resistors closer to 33k.

  • in reply to jc2048

      wrote:

     

    Are you going to make what you've got work first? If you were to over-compenstate for the summing-node bias current, it would lift the 0A point so that the DAC could control it (currently, the DAC has to go negative to get there, which it obviously can't do). 33k in place of R2 and R4 might do it - the 0A point should then need a DAC output of a few mV above zero. (If not, try 30k and then 27k until it comes in range.) You could then do some measurements to see how linear the whole thing was over the full range of current and how much it wanders around as the temperature changes.

     

    BTW. Thanks for the boards. They arrived a couple of days ago.

    I want to try and do that before replacing the opamp. Reworking resistors is a little more forgiving on my pcb than replacing opamps a few times.

    I'll check my parts bin and see if I have something that will work.

    Driving the DAC with an offset is trivial. If it would mess with linearity that would make things more complex though.

  • in reply to Jan Cumps

    got a good replacement for the opamp?

    I was intending to try an OPA4192. It's not available as a wide SOIC, but I figured I could buy the narrow one and extend the pins on one side quite easily.

     

    Are you going to make what you've got work first? If you were to over-compenstate for the summing-node bias current, it would lift the 0A point so that the DAC could control it (currently, the DAC has to go negative to get there, which it obviously can't do). 33k in place of R2 and R4 might do it - the 0A point should then need a DAC output of a few mV above zero. (If not, try 30k and then 27k until it comes in range.) You could then do some measurements to see how linear the whole thing was over the full range of current and how much it wanders around as the temperature changes.

     

    BTW. Thanks for the boards. They arrived a couple of days ago.

  • in reply to Jan Cumps

    LT1058SW - Quad, JFET Input Precision High Speed Op Amp ?

     

    Linear Technology - Product Page

     

    Features
    • 14V/µs Slew Rate: 10V/µs Min.
    • 5MHz Gain-Bandwidth Product
    • Fast Settling Time: 1.3µs to 0.02%
    • 150µV Offset Voltage (LT1057): 450µV Max.
    • 180µV Offset Voltage (LT1058): 600µV Max.
    • 2µV/°C VOS Drift: 7µV/°C Max.
    • 50pA Bias Current at 70°C
    • Low Voltage Noise:
      13nV/rtHz at 1kHz
      26nV/rtHz at 10Hz

    imageimage

    image

    around $10 for a single part.

  • in reply to Jan Cumps

    , , got a good replacement for the opamp?

     

     

     

    The one we're using now, TLE2144, has a SOIC Wide Body 16 pins footprint. It would be ideal if there was a good drop-in replacement.

     

    imageimage

  • in reply to Robert Peter Oakes

      wrote:

     

    ...

    Its gain immediately after a step change on its input will be about 0.3 (Yes less than 1) but then rapidly head toward open loop gain if the expected current is not met

     

    If the DAC is set to zero and your getting 443mA then you should have 866mV across the 2ohm sense resistor ??, did you change the parameters part way through as you show 22mV which would equate to 11mA

    I had the same components as in your design. The sense resistor = 0R05.

  • in reply to Jan Cumps

    I just placed the 680K resistor R32 back. It brings the current when DAC1 = 0 V to 212 mA.

     

    image

     

    Measurements:

     

     

    DAC set0DAC out0.000VR2 left0.000VR4 left-0,065VU3A +0,017VU3A -0,022VU3A out3,210VR7 righ0VR8 right-0,011VU3C +0,078VU3C -0,078VU3C out-0,065V

     

    Let's search for a drop-in OpAmp replacement ...

  • in reply to Jan Cumps

    The op-amp pin out is an industry standard so should be easy to find one that fits, not just from TI but many others

  • in reply to Robert Peter Oakes

    Loads of things to try.

     

    The balancing that John suggested earlier for UC3 (the 680K from + to ground) settled the bias difference fairly well, but I believe it changes the gain from -7.8 to -6.8 (am I wrong)?

    I'll go and purchase a resistor and capacitor 1206 "assorted values" set so I have enough components to experiment with and follow along with what both of you are suggesting. A different OpAmp may be rough - unless we find one with matching footprint ...

     

    (Also: not going to happen in the next 2 weeks because business travel)

  • in reply to Robert Peter Oakes

    Forgot to include a scratch diagram I think simplified image

    image