Programmable Electronic Load - Power Stage

These may be viable candidates Precision Op Amps | Products | Operational Amplifiers | TI.com

there all between 20 and 100nA input bias and should have the voltage range, I did not go lower in nA as there getting more expensive... much more expensive. Of course were using a standard package layout so ones from ST, Linear etc could also work.

So a bit of re hashing my thoughts in case I got it wrong somewhere

• The Op Amps are running with +12V and -5V
• The Analog 0V is the MOSFET Source and the Current Sense + (There all the same or should be), this means that Input to R7 should always be Zero no matter the current flowing through the sense resistor.
• With a U3C design gain of -7.8 (Its - only because the - input goes negative as the current increases) , and assuming the op-amp can go close to rails, it should respond to an input of (12V/7.8) = 1.53V to (-5/7.8) = -0.64V so lets just say -500mV to 1500mV
• The original design expected there to be a Vref of 2.048V and therefor the input was set for 0-1.95V = 0-5A, into a 50mOhm sense resistor = 250mV with a U3C gain of 7.8 gave out of U3C 0 to -1.95V. of course this can be adjusted as needed by changing the SP and or the Sense resistor for different ranges. this counters through the summing resistors the set point. This then after inverting can be read with the ADC again assuming a vref of 2.048V means we dont hit an over range under normal use.
• If the input to the + integrator is positive (The - is tied to analogue 0) then its output will ramp up allowing the MOSFET to turn on more (Assuming something else is not stopping it), note the integrator does not drive on the MOSFET, it simply does not drive it off so much, the integrator is only able to turn off the MOSFET.
• As the MOSFET turns on, the sense goes more negative causing the summing node to go negative until it goes below 0V, at this point the integrator should switch direction and start ramping down. Once equilibrium is found, the integrator will probably hunt very slightly as it is running with open loop gain in a static condition.

The conditions mentioned could be caused by simply the input BIAS currents , I did some digging and found a similar design from Agilent (More complex) and it was using AD706 opamps that have only 200nA input bias current, 4-5 times less basically

http://www.analog.com/media/en/technical-documentation/data-sheets/AD706.pdf

The pull up was also 15V2, through a 9.1V zener, then off to the fet gate via the 4.7K resistor so pretty much the same as we have. only we have 12V and 6V zener......

So we could drop the summing junction resistors to as low as 10 - 20K if needed, this will shrink the effect of the input bias currents by a factor of 10

I still need to re-build this circuit to test for myself but these are my thoughts based on brushed cobwebs and re working the design

U3C input values indicate there is a negative current flowing ( U3C + is higher than - )

I looks like U3C is working correctly based on a gain of 7.8 and the inputs you show, its output is correct within the error of the DMM

Based on the values you show,

there is 820nA flowing from U3A+ through R4 (-67mV + 17mV)/100,000 ?

and 170nA through R2

Total current flowing out of U3C+ being 1uA give or take.... ok 990nA

U3C- would have to be 17mV/18000 = 944nA

looking at the data sheet

That falls just on the typical input bias current of -0.8uA..... Dam it

Also U3A is an integrator so its output will never be still, so there should be a very slight oscillation as it maintains the status quo, aka its gain is that of the open loop in static conditions so it cant just be sitting at 3,304

Its gain immediately after a step change on its input will be about 0.3 (Yes less than 1) but then rapidly head toward open loop gain if the expected current is not met

If the DAC is set to zero and your getting 443mA then you should have 866mV across the 2ohm sense resistor ??, did you change the parameters part way through as you show 22mV which would equate to 11mA

My only reasoning for not wanting to lower the 100K resistors it to maintain protection of the OP Amp etc if for some reason the shunt (Current Sense ) goes open or fet goes short, I had this happen on my manual version and it fried every thing except the VREF, an expensive Vishay 4 terminal shunt is now open circuit and I had to replace the op-amp and the mosfet too.

The idea behind the 100K was to limit the current, even with say 60V load supply to under the MAX current of the protection diodes in the OPAMP. now with the back to back diodes etc, perhaps it is now overkill and we can lower the value ?

So it was a careless mistake on my part by overloading the FET with dissipating too much power, this then caused it to go short.

Possibilities I can see for dealing with the bias current

1) Use a more appropriate op-amp - choose a device with a bias current a thousand times less and the problem largely goes away (though it will then unmask other problems as you try to further increase the accuracy)

2) Change both R2 and R4 to 36k. (In parallel they then match the 18k of R6.) You may also want to change C4 (something like 270pF or 330pF might do) to return the time constant of the differentiator back to what it was. [However, Peter wasn't keen on lowering the 100k resistor value, so you might want to talk to him about it first.]

3) Change R6 to 50k (and also adjust R34 to 13k and C8 to 1.8nF to keep the AC gain and the time constant roughly the same)

4) Ask one of the experts here how they would do it (I'm just giving you textbook stuff - I don't have much real experience of any of this - whereas there are people here who do it for real).

5) Use a more appropriate op-amp. (Sorry, I seem to be repeating myself.)

Measurements with the DAC set to 0.

So, it's working when you close the loop. Yippee!

"I still have to do measurements on the OPAMP 3C and 3A to see what's causing this ..."

Same reason as with the other two op-amps; it's the bias current you haven't yet looked at - the one at the summing point between the two 100k resistors.

The DAC output is 0V. The integrator op-amp is working to make the summing node the same as the other op-amp input. Let's pretend the other input is perfect and doesn't have a bias current and so (at DC) sits at 0V (that isn't actually true, but we can come back to this in a moment). So, if the DAC is 0V and the input pin is 0V, the current in the 100k resistor between them is 0uA. Where, then, does the bias current out of the pin go? It flows through the other 100k resistor. For that to occur, the other end of that resistor would have to be held at -0.1V (if the bias is 1uA) and for that to happen there needs to be an output current flowing to feed back that voltage. So the output won't ever go to 0A (unless your DAC output could go negative, of course) because there always needs to be some voltage fed back to counter the bias current. In practice it won't be quite that bad because the other input to the integrator also has a bias current which partly counters the effect when it flows through the resistor to ground. If you want to stick with this op-amp, you need to deal with the bias current in a similar way to what you did with the other two, however it may be a bit more complicated because of the integrator capacitor.

First experiences.

The FET reacts on the DAC setting.

Below is an example - I put my PSU to 3V and a 2 R resistor in series -

Sending 7090 to the DAC and enabling the input sends 4.014 V to the GATE of the FET.

The current is 1A.

I don't get the current close to 0 A at the moment. When setting the DAC to 0, I get 0 V out of the DAC, but 3.887 V on the gate of the FET.

This results in a current of 0.443 A. I can't get the drive lower.

I still have to do measurements on the OPAMP 3C and 3A to see what's causing this ...

The heat sink also placed.

I have no excuse to hold off the design of the eLoad at this moment. All critical components are in and mounted.

The first goal now is to get it as good as Robert Peter Oakes' original analog design, with the added programmable control.

Very nice