In my first "extra credit" blog, I ventured into understanding more about the various types of supercapacitors and the datasheet characteristics of the supplied Cornell Dubilier components.
In this second “extra credit” blog, I’ll be looking into the process of measuring capacitance and equivalent series resistance (ESR) or sometimes also known as internal resistance (IR). I’ll develop a couple of scripts and spend almost the whole week measuring supercapacitors and analysing the data.
Table of Contents
Why Not Use an LCR Meter or DMM?
When it comes to measuring capacitors, one of the first items you might be thinking of using is an LCR meter or a digital multimeter.
But in reality, such meters are often not a good choice for measuring supercapacitors. This is because most of these meters top out at 10mF or even less. This is not enough for supercapacitors – the smallest in our kit is 100mF and the largest is 40000mF to put it into perspective.
The second reason is that many of these meters cannot handle charged capacitors. Lithium-ion (LIC) hybrid supercapacitors will be charged at all times in normal operation and thus cannot be measured on such meters without potentially causing damage. Even with ordinary electric double-layer (EDLC) supercapacitors may hold sufficient residual charge even at low voltages that they could stress the meter.
But all is not lost … there are other ways of measuring capacitance and the LCR meter may not be entirely worthless.
Instead, as supercapacitors are so big, the measurement techniques used are instead share more similarity with batteries. Ideally, the use of a source measurement unit (SMU) is required for accurate measurements.
Cornell Dubilier’s Technical Guide gives a few methods, however, the constant current method is surprisingly confusing.
The “Charge and Discharge Method” suggests a rate of 10mA/F with a five-minute dwell time.
Later on, the same document suggests a rate of 1mA/F with a thirty-minute dwell time. The measurement voltage V1/V2 are stated as 70% and 30% in text, but then labelled as 80% and 40% below the diagram. The diagram itself illustrates a 5-minute dwell time.
Not satisfied with this, I consulted the AVX datasheets which had much better guidance.
The IEC method for measuring capacitance uses 4*C*Vr as the current in mA (i.e. 10.8mA/F to 22mA/F depending on voltage). The capacitor is charged to rated voltage and disconnected. Then after 30 mins, it is discharged at constant current with 80% and 40% voltage points used for computing capacitance. That being said, this was not the method I employed as there was another method which seemed more convenient.
Measuring Equivalent Series Resistance (ESR)
Another key parameter for capacitors is their equivalent series resistance (ESR) or internal resistance (IR), the latter terminology being more commonly used with batteries. This can be imagined as a “restriction” that limits the speed by which the capacitor can charge or discharge. This also leads to energy dissipation as heat which can shorten the life of the capacitor as well. Lower ESR means better electrical efficiency, lower self-heating, better peak current capability and lower voltage drop under load. There are two common methods – AC ESR and DC ESR which gives different values and are not interchangeable. Usually the DC ESR is greater and represents the voltage drop you would experience under load, while the AC ESR tells us a bit about the internal electrochemical status of the capacitor without causing any net charging or discharging.
The AC ESR is ordinarily performed by injecting a small symmetrical 1kHz AC signal into the capacitor and measuring the current and voltage magnitude to determine the resistance. In this case, it actually can be acceptable to use an LCR meter on discharged EDLC capacitors for this purpose as the ESR value is usually within the range of the meter even if the capacitance is not. However, there are no guarantees.
Instead, ideally you should use an LCR meter that can handle voltage across its inputs. Thankfully, I have one in the form of the B&K Precision BA6010 Battery Analyser – don’t be fooled by the name, it’s basically an isolated 1kHz AC LCR meter that can handle a voltage up to 60V across its input making it acceptable for measuring even charged LICs.
You might be surprised to see the capacitance is not measuring “correctly”. This is actually proper behaviour – because the capacitor doesn’t have anywhere near as much effective capacitance at a frequency as high as 1kHz. In essence, supercapacitors are too “slow” to react at such high frequencies – in fact, it’s been stated in several datasheets that they’re not even meant to be used for smoothing out ripple as that can shorten their life expectancies dramatically.
The DC ESR can be determined through charge and discharge tests similar to the test for capacitance, although the rate and timings can be different depending on which procedure is used.
Cornell Dubilier’s Technical Guide recommends a rate of 1mA/F with holding the voltage for 1 minute. The values for V1 and V2 are not given, and are assumed to be arbitrary (in the ideal case, this would be true).
I consulted the AVX datasheets again, in which they proposed a six-step DC ESR and capacity measurement methodology. This takes a two-cycle approach with a rate of 75mA/F instead and seems preferable. However, the short dwell time may mean that some supercapacitors may not have the time to charge fully.
Experiment #2: Capacitance & ESR Measurements
It’s time to actually put this theory into practice and measure the whole set of capacitors to get some baseline data. At least, this should be able to tell us whether the LICs suffered any permanent damage. Testing took a lot of time – looking at the scale on some of the graphs, depending on the rate and voltage of the capacitor, a single run could take two to three hours.
For this experiment, I used the Keithley 2450 SourceMeter as my measurement instrument along with two scripts I have developed that implement a “fast” method based on the AVX datasheet and a “slow” method which is based on the IEC/CDE recommendations.
In the case of EDLC, the script first discharges the capacitor to zero (prior to logging), charges the capacitor from zero, dwells for 60s, discharges to V/2, rests for 60s, charges to V, dwells for 60s, then discharges to 0.1V. Capacitance values are calculated based on the V to V/2 time.
In the case of LIC, the script instead will discharge the capacitor to 2.5V (prior to logging). The other steps are similar but instead of V/2, a lower limit of 2.5V is used. Post-test, instead of discharging, the capacitor is recharged to 3.6V for storage. Capacitance values are calculated based on V to 2.5V time.
Using the same data, the DC ESR was determined from the samples around the load-step. This is repeated for both down-slopes so each “fast” run resulted in two values for capacitance and DC ESR.
The slow method was implemented with a discharge to 0V prior to commencement, a 30-minute dwell time while remaining connected to voltage (to more thoroughly charge the supercapacitor) and discharge to 0.1V. Capacitance is calculated between 0.8*V and 0.4*V. As a result, this is not strictly adherent to IEC methodology but is more convenient.
A similar change was made for LICs in the slow method, a discharge to 2.5V prior to commencement, discharge limited to 2.5V (as the end-point) and recharge to 3.6V for stage post-test.
Connections were initially done as two-wire with clips, with null compensation for lead resistance. Later tests were performed in four-wire mode to remove lead resistance effects, despite the unwieldy nature of such connections. Polarity was doubly-verified prior to each test to ensure no damage to the supercapacitors. Before anyone says it - yes, I know putting stress on capacitor legs is not a good thing!
Keithley TSP Scripts
The results were gathered by modifying a capacitance test script I first wrote for my Keithley 2450 SourceMeter RoadTest.
The first script implements a modified “fast” method at 75mA/F (or 7.5mA/F for LICs) with 60s dwell time and two cycles measuring capacitance between rated voltage and half-voltage (or 2.5V for LICs) as previously seen in AVX datasheets.
The second script implements a modified “slow” method at 1mA/F with 30m dwell time and a single cycle as recommended by IEC and CDE, measuring capacitance between 80% and 40% (or 2.5V for LICs) of the rated voltage.
Unfortunately, neither script will directly print out the DC ESR, however, it could be modified to do so. I instead opted to analyse the stored CSVs for the data, however, computing ESR from the slow script is not recommended as low-currents produce small voltage drops and this results in large measurement errors. The higher 75mA/F rate produces much more reasonable measurements.
Capacitance & ESR Results
The graphs in the methodology show typical results for “healthy” examples of supercapacitors. The overall data values are tabulated below:
The capacitor part numbers in red are the units that were over-discharged. Tests done with a * indicate two-wire mode was used, with ` indicating that the null resistance compensation was performed to take away lead resistance. Tests indicated with ^ are done in four-wire mode.
High AC and DC ESR was found in measurements of all EDC and EDS parts which are coin-cell style supercapacitors. This is perhaps not unexpected as they are intended for memory backup (i.e. slow drain) applications rather than peak current pulses and as a result, no DC ESR is provided in the datasheet. However, it is interesting to see the big discrepancy between AC ESR values.
Other supercapacitors appeared to be within range for AC ESR, however, DC ESR showed some marginal readings for DSF256Q3R0. Interestingly, the over-discharged LICs all showed significantly elevated ESRs (VMF406M3R8, VMF256M3R8) which appear inversely-correlated to the state-of-charge as received (i.e. deeper discharge = higher ESR). One of the not-overly-discharged LICs (VPF406M3R8) also seems to have a consistently higher DC ESR than datasheet which was slightly surprising, but not as significant as the over-discharged units.
Capacitance values as measured using the “fast” method shows all EDC/EDS coin-cells and LICs as having less capacitance than rated, sometimes significantly so. I suppose this is because there is insufficient time for the supercapacitors to “soak” a full charge, especially for the coin-cell type.
Repeating the test with the “slow” method finds all EDC/EDS coin-cells to now comply, while the radial-type DGH/DSF series are all “over-performing” somewhat. Unfortunately, all LICs (VMF/VPF series) are under-performing even with the 30-minute dwell time and I am unsure as to the cause. In some cases, the results of this slower test were even worse than the fast mode – suggesting something may have happened to the capacitor in test.
Looking closely, it is clear that all supercapacitor charging, even EDLC, are not entirely linear, so the choice of start- and end-points can have an influence in the computed capacitance figures.
Recovery of the over-discharged LIC actually results in a very non-linear voltage curve under constant-current charging. This suggests to me some sort of electrochemical process may be happening. The performance is inconsistent.
However, on subsequent charges, it seems to be have more normally, suggesting the “recovery” charge is permanent in reverting the state of the capacitor, but this may not recover the full performance especially if the over-discharge is repeated.
Bonus: Solar Panel Arrives!
Another key event in this challenge occurred this week – I received the second package containing the solar panel.
The package was unexpectedly light, and in the journey to Australia, suffered a bit of crushing.
Thankfully there was not much inside – the solar module is ensconced inside bubble wrap.
The cell is a OSEPP SC10050 which claims to be a 5V 100mA monocrystalline solar cell with an “Arduino-Compatible” barrel plug termination (which I would assume is a 2.1mm ID 5.5mm barrel plug with centre positive). This would imply a power of 0.5W.
The surface of the unit reminds me a bit of a solar garden light – the encapsulation is some rather hard plastic of some sort. A short length of cable is available, however, I can’t see anyone using this with an Arduino directly purely because anyone who’s used solar knows that the output will vary as the sun moves across the sky, as any intervening clouds get in the way, or anything else for that matter (e.g. a bird). The rating is likely not a stable output and will depend on factors such as sun, tilt, temperature and load.
Looking from the rear, it seems the cells may have been soldered to a PCB-like substrate. The wires come out of a plastic box on the rear. This leads me to ask the question – is there any regulation?
Popping the cap off … it’s clear that there’s nothing but silicone and hot-glue. No regulation at all, nor any smoothing in the form of capacitors. This is as promised – a raw solar module, but without any Vmp/Voc/Isc data available.
Doing some quick measurements to verify the power rating – each cell measures 52mm x 6mm and there is a total of 10 in series. As each cell puts out about 0.5V to 0.6V, the output will be expected to lie in the 5-6V range. In terms of total power, the total cell area of 3120mm2 implies a solar input of 3.12W for the area under AM1.5 1000W/m2 conditions. With average monocrystalline cell efficiencies ranging from 15-24%, this suggests the output will range from 0.468W to 0.749W. In all, the numbers seem to add up, which is great!
Measuring the capacitance and equivalent series resistance of a supercapacitor may sound like something straightforward, however, it is not just as simple as hooking one up to an LCR meter for a number of reasons. In fact, the method by which you measure the capacitor has an influence on the resulting measurements!
Having chosen both a “fast” and “slow” measurement method alongside an isolated LCR meter, I found that EDS/EDC coin-cell supercapacitors to have a rather high internal resistance. This makes sense, as they are used for memory back-up rather than pulse-power applications. The DGH/DFS radial supercapacitors generally measured favourably. The hybrid VMF/VPF LICs were a mixed bag, in part because some were received damaged. However, even those that weren’t damaged didn’t always measure their full capacitance value or as low of a DC ESR as claimed even under the slow test regime. The cause is unknown at this time and their performance seems somewhat inconsistent. Further investigation will be necessary.
The damage to the LICs was definitely witnessed in the odd charge curves initially and in the noticeably higher ESR and reduced capacity. I would venture to guess that this damage would likely be permanent and may be cumulative in case further over-discharges occur.
Finally, the solar panel has arrived. While it reminds me a bit of the types used for solar garden lighting, I’ve checked the cell area and it seems that it is likely to meet the stated output specifications while also not having any smarts or regulation on-board.
While I did want to cover the leakage current of the supercapacitors in this section, I’m afraid it will have to be in the next part. These experiments took much longer than I had anticipated, but I should be able to report on a few other findings as well in the next instalment.
[[What’s Super about Supercapacitors: Blog Index]]
- What’s Super about Supercapacitors? – Part 1: Me and the Kit
- What’s Super about Supercapacitors? – Part 2: Types, Vendors, Safety & Specifications
- What’s Super about Supercapacitors? – Part 3: Measuring Capacitance & ESR
- What’s Super about Supercapacitors? – Part 4: Measuring Leakage, Sizing a Solution & Lifetime
- What’s Super about Supercapacitors? – Part 5: Safety Under Abuse & Power Back-Up Application
- What’s Super about Supercapacitors? – Part 6: Solar LoRaWAN PM Sensor, Low-Temps, Imbalance, Cyclic & Short Circuit Life, LED Blinker
- What’s Super about Supercapacitors? – Part 7: Quite a lot, actually! (Final)