Audio Synth #4 - Use PWM to control LED

Table of Contents

1. Audio Synth #1 - The project
2. Audio Synth #2 - Board introduction and IDE setup
3. Audio Synth #3 - Arduino to CmodS7 COMM Test
4. Audio Synth #4 - Use PWM to control LED
5. Audio Synth #5 - Testing the I2S PCM5102 DAC Decoder Board
6. Audio Synth #6 - Sound generation with CmodS7
7. Audio Synth #7 - Design challenge ends, project continues

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Project:

This is about controlling LED intensity using PWM. My very first attempt at writing Verilog code was to turn on the red LED on CmodS7. You can find the motivation for this LED PWM control example in Note 1 at the end of my Audio Synth #2 blog (to put it in a sentence: use PWD to control LEDs, not solid logic levels.)   /challenges-projects/design-challenges/summer-of-fpga/b/blog/posts/audio-synth-2---board-intro-and-ide-setup

Instead of turning on the red LED using a constant logic 0 level, I will use a periodic signal with a configurable duty cycle. This is done counting the number of positive transitions of the 12MHz clock on CmodS7 to generate an output signal with the wanted duty cycle.

The Verilog module has one input (the 12MHz clock) and one output (the pwm signal that controls the redLED. I also wrote a simple test to make sure that the pwm output is the desired one. 

The constraint file maps the clock input and red LED pins.

The main pwdControl.v module:

The testbench for running the simulation:

And the top file which instantiates the pwdControl module.

To run the simulation, I disabled the top file and set the testbench.v file as top. 

To synthesize, route and generate the bitstream file, I disabled the testbench.v and set the top file as top of the source hierarchy. Not sure this is the right way to do it, it worked for me but I have a feeling that for more complex projects, one or more separate Verilog projects might be needed (probably this can be done with a clever source file directory structure and code organization.)

Here are two screen capture of the simulation. The first one passes parameters   .COUNTER_WIDTH(3) and .MAX_COUNT(7). The second one has   .COUNTER_WIDTH(4) and .MAX_COUNT(10). 

So it seems the code works the way it is supposed to.

Github Repository

https://github.com/a3333333/Summer-of-FPGA/tree/main/pwmLedControl

This time, instead of checking into github the whole Vivado project, I only checked in the source and the constraint files. If you want to try on the code, you can create an empty project for Cmods7 board and add the files from github. 

I generated the bitstream file and programmed the FPGA with different values of MAX_COUNT parameter and observed the brightness of the LED. It works as expected (a higher MAX_COUNT means a dimmer LED).

Concepts: PWM, duty cycle, parameter passing in Verilog, simulation & testing

Note1: 

This is a quote from section 6 of CmodS7 reference manual  https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual

“Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the RGB LED. Driving any of the signals to a steady logic '0' will result in the LED being illuminated at an uncomfortably bright level. This can be avoided by ensuring that none of the RGB signals are driven with more than a 50% duty cycle. Using PWM also greatly expands the potential color palette of the RGB LED. Individually adjusting the duty cycle of each each color between 50% and 0% causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.”

Changelog:

01/30/2022 - added Note1