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A highly flexible, rugged, System-On-Module (SOM) based on the Xilinx ZynqRegistered-7000 All Programmable (AP) SoC. It offers the flexibility to migrate between the 7010, 7015, 7020, and 7030 Zynq-7000 AP SoC devices in a pin-compatible footprint.
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Technical Specification

The PicoZed module contains the core requirements to support SoC design including memory, configuration, Ethernet, USB, and clocks. It provides easy access to over 100 user I/O pins through three I/O connectors on the backside of the module. These connectors can support dedicated interfaces for Ethernet, USB, JTAG, power and other control signals, as well as the GTP/GTX transceivers on the 7015/7030 models. The transceiver based 7015 and 7030 versions of PicoZed are a superset of the 7010/7020 version, adding four high-speed serial transceiver ports to the I/O connectors. You can design your own carrier card, plug-in a PicoZed, and start application development with a proven Zynq-7000 AP SoC sub-system. Product Brief (Datasheet)

Click on the images to enlarge

7010 SOM Front
7010 SOM Front
7010 SOM Back
7010 SOM Back
7015 SOM Front
7015 SOM Front
7015 SOM Back
7015 SOM Back
7020 SOM Front
7020 SOM Front
7020 SOM Back
7020 SOM Back
7030 SOM Front
7030 SOM Front
7030 SOM Back
7030 SOM Back

Hardware Specification

Specification Description
SOC OPTIONS
  • XC7Z010-1CLG400
  • XC7Z020-1CLG400
  • XC7Z015-1CLG485
  • XC7Z030-1SBG485
MEMORY
  • 1 GB of DDR3 SDRAM
  • 128 Mb of QSPI Flash
  • 4 GB eMMC
COMMUNICATIONS
  • 10/100/1000 Ethernet PHY
  • USB 2.0 PHY
USER I/O (VIA THREE BOARD-TO-BOARD CONNECTORS)
  • 7Z010 Version
    • 113 User I/O (100 PL, 13 PS MIO)
    • PL I/O configurable as up to 48 LVDS pairs or 100 single-ended I/O
  • 7Z015 Version
    • 148 User I/O (135 PL, 13 PS MIO)
    • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O
    • 4 GTP Transceivers
  • 7Z020 Version
    • 138 User I/O (125 PL, 13 PS MIO)
    • PL I/O configurable as up to 60 LVDS pairs or 125 single-ended I/O
  • 7Z030 Version
    • 148 User I/O (135 PL, 13 PS MIO)
    • PL I/O configurable as up to 65 LVDS pairs or 135 single-ended I/O
    • 4 GTX Transceivers
OTHER
  • JTAG configuration port accessible via I/O connectors
  • PS JTAG pins accessible via I/O connectors
  • 33.33 MHz oscillator
SOFTWARE
  • Linux BSP and reference design

Reference Designs

PicoZed FMC Carrier Card V2

Tutorial 01 Build the Zynq Hardware Platform

Tutorial 02 First Application - Hello World

Tutorial 04 FSBL and Boot from QSPI and SD Card

Tutorial 07 PL SPI Controller

Transceiver Clock Programming Reference Design

FMC-HDMI-CAM + PYTHON-1300-C Vivado HLS Reference Design

FMC-HDMI-CAM + PYTHON-1300-C SDSoC platform

PCIe End Point Reference Design

Development Using Ubuntu Desktop Linux

These tutorials provide a means to integrate several different technologies on a single platform. Using the Avnet target boards, we have the power of ARM processors, combined with the unrivaled flexibility of Xilinx programmable logic to implement custom hardware systems. We use a Linux kernel as the foundation operating system running on the processor cores which enables a very large ecosystem of software to be run on our development kits. Virtual machines can provide a very convenient Ubuntu development environment for building the hardware platform and cross-compiling software to target the Processing System.

PCIe PIO Demo

PicoZed FMC Carrier Card V1

Tutorial 01 Build the Zynq Hardware Platform

Tutorial 07 PL SPI Controller

Restore/Upgrade QSPI Factory Image

Open Source Linux Ethernet Performance Test Tutorial

PCIe PIO Demo

Technical Documents

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