Parallella $99 board now open hardware on Github

Although Adapteva are still fulfilling their Kickstarter committment, their shop is already open for preorders of the 16-core Epiphany board for November delivery.  Three options appear to be available:

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Morgaine Dinova wrote:

 

If "No GPIO" means none, zero, zilch, that doesn't appear very enticing, I must say.  If this describes the situation accurately, the range of application of the basic board will be a lot narrower than expected.  And if the Zynq-7020-based Parallella-16 costs $199, then the price of the Parallella-64 is probably going to be very unfriendly.

Given there's an 'optional upgrade' for the GPIO connectors it seems likely that the difference is simply down to installing the connectors.  Any volunteers to hand solder four of those ?

In some ways you can see the reasoning, not having them will not prevent you doing software things on the Epiphany processor.  If you really want gpio, and don't care so much about the Epiphany there are probably better boards.

Am I correct in thinking that the only difference between the 7010 and 7020 is more FPGA space ?  If so, what's this board really meant to be, a dev board for parallel processing on the Epiphany, or an FPGA dev board ?

John Beetem wrote:

 

The US$99 board gives me the option of using lower-cost GPIO connectors if I don't need the speed of the Parallella's usual Samtec BSH-030-01-FDA sockets, or I want other options.  Or I can just populate the one that's connected to Zynq and leave the others unpopulated, saving 75% of the part cost.  Always nice to have options.

Ah that's good to hear.  So it seems the "No GPIO" in the dropdown list for the $99 version doesn't really mean what it says, fortunately.  That's a relief, and I'm sure not only to me.

Morgaine Dinova wrote:

 

The FPGA in the Zynq undoubtedly has a maximum throughput vastly exceeding that of the ARM cores, based on our background knowledge of typical FPGAs.  This means that the Zynq's dual Cortex-A9 cannot be anywhere near optimum for feeding data through the  interface at the highest rate the FPGA can probably sustain.  Because of the Zynq's AXI Bus (shown on the whitepaper I linked in post #24), the Zynq is probably very efficient at this, but in the end the data is still being generated by a pair of lowly Cortex-A9 cores clocked at 800MHz.  The AXI Bus reduces bottlenecks but it can't speed up the ARMs.

I believe you can also use the the FPGA fabric to talk to the system buses directly without going through the ARM cores, i.e., the FPGA can DMA to shared DRAM and also to peripheral devices like Gigabit Ethernet.  This way you can build very high performance data processing beyond what an ARM core can handle, and basically use the ARM to run control software with modest processing requirements.

John Beetem wrote:

 

I believe you can also use the the FPGA fabric to talk to the system buses directly without going through the ARM cores, i.e., the FPGA can DMA to shared DRAM and also to peripheral devices like Gigabit Ethernet.

While true, the Zynq doesn't have a monopoly on DMA.  Any reasonable ARM system can be expected to feed its DMA controllers at close to memory rate, and even Cortex-M* microcontrollers commonly feature crossbar-type internal buses so that different types of data transfer can occur in parallel and DMA controllers aren't starved by bus arbitration.  In other words, far cheaper ARMs could keep the Epiphany eLinks equally busy through DMA.

Regarding Ethernet, that really comes down to DMA again.  There is no room in Epiphany core local memory (just 32KB per core) for full TCP/IP stacks, so the host will have to handle the networking, extract the data out of the protocol payload, and DMA can then fish it out of memory for feeding Epiphany.  But again, the Zynq doesn't have any special advantage for this since gigabit MACs are quite common in modern ARM SoCs (less so gigabit PHY, sadly).

Morgaine Dinova wrote:

 

Regarding Ethernet, that really comes down to DMA again.  There is no room in Epiphany core local memory (just 32KB per core) for full TCP/IP stacks, so the host will have to handle networking, extract the data  out of the protocol payload, and DMA can then fish it out of memory for feeding Epiphany.  But again, the Zynq doesn't have any special advantage for this since gigabit MACs are quite common in modern ARM SoCs (less so gigabit PHY, sadly).

You could probably do wire-speed TCP/IP in the FPGA fabric, using block RAM for table look-up.

How's the power consumption for GBE PHYs these days?  Maybe it's better to leave them off SoC so the chips don't get too hot.

John Beetem wrote:

 

You could probably do wire-speed TCP/IP in the FPGA fabric, using block RAM for table look-up.

TCP/IP protocol implemented entirely in FPGA block RAM?  You jest ... I hope.

No doubt small and well-defined auxiliary functions could be implemented in the FPGA fabric as part of a TCP offload engine (which are quite common nowadays), but to implement the whole thing in hardware simply doesn't make engineering sense because most parts of TCP/IP are not in the high-speed pathway or are rarely executed.

How's the power consumption for GBE PHYs these days?  Maybe it's better to leave them off SoC so the chips don't get too hot.

That was just poor phrasing on my part.  I meant that gigabit PHY are less common on ARM boards even when the host SoC provides gigabit MAC.  Your point about heat is a good one.  Gen0 Parallella recipients were complaining quite a lot about heat.

Morgaine Dinova wrote:

 

John Beetem wrote:

 

You could probably do wire-speed TCP/IP in the FPGA fabric, using block RAM for table look-up.

TCP/IP protocol implemented entirely in FPGA block RAM?  You jest ... I hope.

 

No doubt small and well-defined auxiliary functions could be implemented in the FPGA fabric as part of a TCP offload engine (which are quite common nowadays), but to implement the whole thing in hardware simply doesn't make engineering sense because most parts of TCP/IP are not in the high-speed pathway or are rarely executed.

I'm talking about the core packet processing functions like CRC checksum and port numbers and window management.  I'm also talking about IPv4 since I don't have experience with IPv6.  However, since modern wire-speed routers are implemented in hardware, there's no reason you can't do this with a decent FPGA since managing an end-point is a lot easier than routing.  In fact, you can buy TCP/IP IP for various Xilinx FPGAs.

John Beetem wrote:

 

However, since modern wire-speed routers are implemented in hardware, there's no reason you can't do this with a decent FPGA since managing an end-point is a lot easier than routing.

I think you meant the opposite, that routing is a lot easier than managing an endpoint.  Routing in hardware needs to handle only the IP layer and can ignore all higher-level detail, which is just payload data at the IP level --- that's why good routers can route frames back-to-back even on 10gig.  The routing management protocols and ICMP only come into play at exception or change points, so that's typically left to CPUs to handle at their leisure in all but the highest end backbone routers.

At the endpoints, the entire protocol stack comes into play, which is a heavy burden indeed.  TCP offload engines commonly dedicate an embedded CPU to the task rather than hardware, although as we both mentioned, simple functions like CRC are very commonly implemented in hardware, often as a dedicated instruction in the SoC.

That iTOE Verilog for Virtex and Spartan doesn't look like open source to me.

@Morgaine and John,

I haven't quite got to full TCP/IP in the fpga yet but I'm currently using a Lattice ECP3 to generate multi fragment UDPs sent out at wire speed to GBE, (external Marvell phy and it runs pretty hot  - which answers an other question). I can't see that it would ever make sense to do all of the work in the FPGA  - things like ARP don't need that kind of speed.

I would love to get my teeth into some TCP acceleration in the FPGA but it is very expensive in terms of development time and we have already hit issues with common GBE network components (like switches) which cant actually handle wire speed data unconditionally - and the conditions are not well specified.

One of the problems you hit with sharing the network stack between processor and FPGA is that you end up writing the entire stack, parts in C and parts in VHDL or Verilog - that's why so far we've kept our end very simple with support for UDP, IP, ARP and not much else.

The phy uses more power than the FPGA and the processor (STM32F407).

MK

John Beetem wrote:

 

I'm actually quite amused (not ROFL -- more like rocking back and forth holding my knees chuckling) at the idea that US$99 is expensive for a Zynq board in 2013.  Parallella was originally prototyped with a 7020-based ZedBoard, which is still US$395 (US$319 for academics).  [FYI: ZedBoard is now 1 year old and has sold over 3,000 units.]  There's now a 7010-based MicroZed board for US$199.   IMO getting the cost with Epiphany down to US$99 is pretty impressive, even if that's pre-order pricing.

Digilent has announced a Zynq 7010-based board called ZYBO for US$149.  Much friendlier I/O than Parallella, including bidirectional HDMI, 16 bit/pixel VGA, 10/100/1G Ethernet, 512 MB DDR3, and five Digilent PMOD connectors for various I/O cards.  I don't think it has any high-density GPIO connectors, so if you need a lot of GPIO you're probably better off with a MicroZed.  It is nice to see Zynq boards coming down to a reasonable price range.

I suspect that Zynq will never have a reasonable price, meaning the price of mass-market Chinese SoCs.  Like Intel, Xilinx seems to believe that keeping prices sky-high is intrinsic to its self-respect and/or survival, and so the company is not playing the game described by that famous saying "The natural price of all semiconductors is the price of their packaging."

I suspect that Zynq will never have a reasonable price, meaning the price of mass-market Chinese SoCs.  Like Intel, Xilinx seems to believe that keeping prices sky-high is intrinsic to its self-respect and/or survival, and so the company is not playing the game described by that famous saying "The natural price of all semiconductors is the price of their packaging."

Morgaine Dinova wrote:

 

I suspect that Zynq will never have a reasonable price, meaning the price of mass-market Chinese SoCs.  Like Intel, Xilinx seems to believe that keeping prices sky-high is intrinsic to its self-respect and/or survival, and so the company is not playing the game described by that famous saying "The natural price of all semiconductors is the price of their packaging."

Xilinx prices on Spartan chips are very attractive IMO.  If you want to use the latest and greatest and highest performance Xilinx chips in big packages, prepare to pay big bucks.  I'm definitely not the target demographic for those chips.  If you wait a few years for them to get the kinks out of the process, you can get Spartans for great prices.  But it's hard to get down to the "price of the packaging" because an FPGA is essentially an SRAM array with some gates attached to it, and SRAM is pretty expensive.

I once nearly throttled a salesman who sold Xilinx chips because he said my designs obviously weren't very "sophisticated".  I held off because I realized that by "sophisticated", he meant designs that required fast, expensive Xilinx chips with high sales commissions.  He didn't mean "using every trick in the book and a few adapted from other books" to fit a complex function into a smallish, not particularly fast Spartan to save big bucks

John Beetem wrote:

 

Xilinx prices on Spartan chips are very attractive IMO.

The words "reasonable" (used earlier) and "attractive" as you've been using them are different to the way in which I prefer to use them.  What they mean to you appears to be "Less costly than I expected them to be", or perhaps "Less costly than they were before".  It has no bearing on their actual cost relative to the state of technology.

If people have gotten used to the latest iLust gadget costing $500, then with the above semantic a price drop to $300 would probably be described as making them "reasonable" or "attractive", despite the fact that it's still bloody extortionate when similar functionality is available for under $100.  Of course there's room for quibbling over quality, but in the case of digital semiconductors that excuse practically evaporates because digital technology without the required noise margins simply doesn't work.

I accept that Spartans can be purchased for not much more than the price of packaging, 3A's all the way down to single digit unit prices, but my comment was really aimed at Zynq, or should have been.

My argument about Zynq pricing would have been stronger if I could point to a native Chinese ARM+FPGA with similar functionality but a much lower price tag, but alas I can't, and I'm not even sure how to  start looking.  (And the documentation might not be in any language I understand anyway.)  Despite this weakness, my gut feeling is that Xilinx is making no effort to bring this family of devices to the mass market (which is entirely a function of price), despite having had ample time to do so since the concept was sprung on the world ages ago.  I think it likes to give this particular product an air of exclusivity (and charge accordingly), which is why it's so hard to find the device listed, priced and in stock.

Parallella seems to be very much an oddball, a product that democratizes Zynq despite Xilinx's best efforts at keeping it away from the unwashed masses.

Morgaine Dinova wrote:

 

John Beetem wrote:

 

Xilinx prices on Spartan chips are very attractive IMO.

 

The words "reasonable" (used earlier) and "attractive" as you've been using them are different to the way in which I prefer to use them.  What they mean to you appears to be "Less costly than I expected them to be", or perhaps "Less costly than they were before".  It has no bearing on their actual cost relative to the state of technology.

 

If people have gotten used to the latest iLust gadget costing $500, then with the above semantic a price drop to $300 would probably be described as making them "reasonable" or "attractive", despite the fact that it's still bloody extortionate when similar functionality is available for under $100.  Of course there's room for quibbling over quality, but in the case of digital semiconductors that excuse practically evaporates because digital technology without the required noise margins simply doesn't work.

 

I accept that Spartans can be purchased for not much more than the price of packaging, 3A's all the way down to single digit unit prices, but my comment was really aimed at Zynq, or should have been...

Well, the first marketing materials for Zynq said "starting at $15" [Xcell Journal 2Q2011] and maybe they'll get down there some day.  As far as comparing to iGewgaws, it's a question of volume.  A technology that sells 10M - 100M/year is going to be a lot cheaper than FPGAs, which rarely get into high-volume devices for the simple reason that if you're going to have high volumes you're better off synthesizing your Verilog/VHDL into a real ASIC.  FPGA proponents talk about "getting an FPGA into a cell phone", but the reality is that the margins aren't there and cell phones don't need the logic flexibility an FPGA offers.  Proponents say "but wait!  the FPGA is reconfigurable!" but IMO it's hard enough to get one design to work in an FPGA, much less a whole slew of them.  This would change if they'd open up the bitstream formats.

I'd be quite happy to get that $15 chip   Maybe someday.  It takes a long time for Xilinx parts to get cheaper, and usually you don't see much price movement on generation N until generation N+1 comes out.  Most of the stuff I read about Xilinx these days is about 3-D chip construction and other ways to make their chips more expensive.  Well, that's probably where they make their money, and Spartan is there because otherwise a competitor would take over the entry level, and then leverage themselves up.  As long as the Chinese stay away from FPGAs, I don't expect much change, and FPGAs haven't reached enough volume to get the Chinese interested.

Back to Zynq pricing, I guess I'm not sticker-shocked because my then-company looked into Virtex II-Pro a long time ago.  Our products were mostly based on PowerPC, so the idea of having PowerPC integrated with an FPGA seemed pretty good.  Then we saw the price tag, and quickly went with a cheap PowerPC SoC and a cheap  Spartan-IIE, interconnected with PCI.

Where FPGAs really stand out IMO is medium-volume applications where designing an ASIC is too expensive and too risky, but the design is not practical without a custom chip.  If it's a communication product where protocols may be evolving (or you need to add others in the future), the flexibility of an SRAM-based FPGA is an excellent match, since you can ship a new release of the hardware with each software release.  FPGA are also great for communication test equipment, where the protocols needed to be tested evolve and you'd like to minimize the effort of updating your equipment.  But it's a medium volume product, though with enough margin that current FPGA pricing is, well, pretty "attractive".

John Beetem wrote:

 

But it's a medium volume product, though with enough margin that current FPGA pricing is, well, pretty "attractive".

Grrrrrr ....

I wonder why in these discussions so many people overlook Lattice. Easily the most fun FPGA company and they DO have FPGAs in phones. Their Ultra Low Density approach fits well with John's definition of sophisticated and is currently delivering a million parts per day at very low (single $ or less) prices.

(MInor rant over -BTW I have no connection with Lattice other than as a customer).

Even though I don't use any Xilinx parts at the moment I think the cost/pricing issue is more complex than just the cost of the silicon. Xilinx (and I assume Altera) spend more on software development than on hardware development. They also spend huge sums on research which makes the mega parts possible. They have to get that back somehow and whilst both companies make a profit I don't think they do much better overall than, for example, Linear Technolgy and nothing like as well as Intel have done. (That's in term sof margins not size).

And much as I like Lattice their approach with simple cheap bits hasn't made them as big as X or A.

I think we'll see the FPGA market grow a lot more - the potential for cheap tiny parts is huge - but tiny is more about price and package - the capability is getting better all the time. I'm already able to get 1000 LUTs for £2 in 100s off but, I think, <<£1 for 100k. The next generation (Lattice 'X03) will expand tiny to cover 640 to 22k LUTs and at lower prices. The space for ASICs gets smaller with each advance of FPGAs - I don't play in the meg chip zone but there is a lot of scope with the cheapo parts.

Hmmm - this has got very off topic - sorry.

MK

I agree with Michael there, and I'd much rather see open source support the underdog than the field leader --- it's easier to gain some influence that way, among other things, and the immoveable leader then feels the lack of love and sometimes reacts.  Look at nVidia as an example of that, against all expectations actually sitting up and taking notice when it got the finger of disrepute pointed at it.

Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer, especially when spelled with an 'O'.

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Readers would get extremely confused if we ever managed to stay on topic.

Michael Kellett wrote:

 

I wonder why in these discussions so many people overlook Lattice. Easily the most fun FPGA company and they DO have FPGAs in phones. Their Ultra Low Density approach fits well with John's definition of sophisticated and is currently delivering a million parts per day at very low (single $ or less) prices.

(MInor rant over -BTW I have no connection with Lattice other than as a customer).

I need to take closer look at Lattice when I've cleared some of my higher priorities.  My general position is that until Brand L opens its architecture there isn't a compelling reason to switch from Brand X or Brand A, but I'm curious to play with iCE40 and MachXO2/3.

Xilinx (and I assume Altera) spend more on software development than on hardware development.

We all know there's a simple solution to that problem, one that Intel and other processor manufacturers figured out a long time ago   IMO semiconductor companies should do what they do well, and let FLOSS do its magic for the rest of the problem.

I earlier gazed into the future and handwaved:

 

"Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer"

Well then I got around to looking at their MachXO3 page and discovered ...

Lattice writes:

 

Integrated Support for the Latest Interfaces - Simplify and optimize your system design using MIPI, PCIe, and GbE hard blocks.

OK, now they really have my attention!   This is a gigabit IoT device on a chip at CPLD prices.

Due "October" ...

Morgaine Dinova wrote:

Michael Kellett wrote:

 

Hmmm - this has got very off topic - sorry.

Readers would get extremely confused if we ever managed to stay on topic.

tts the off topic stuff that makes the messages (threads) so interessting.

Walt

Morgaine Dinova wrote:

 

I earlier gazed into the future and handwaved:

 

"Lattice MachXO2 looks nice, and 'XO3 will probably be even nicer"

 

Well then I got around to looking at their MachXO3 page and discovered ...

 

Lattice writes:

 

Integrated Support for the Latest Interfaces - Simplify and optimize your system design using MIPI, PCIe, and GbE hard blocks.

OK, now they really have my attention!   This is a gigabit IoT device on a chip at CPLD prices.

 

Due "October" ...

I'll save my opinion until I find out what's the cheapest MachXO3 that has PCIe and/or GbE.  For example, you can't get Zynq PCIe until you get up to to the Z-7030, or Spartan-6 PCIe until you get to the XC6SLX25T.