Arduino: now a Single Board Computer!

Walt Gribben has just confirmed the existence of an MMU in our sister thread:

Walt Gribben wrote:

 

theres one big piece of Quark that has been overlooked.  Having worked with Intel architectures for some time now, I'm familiar with the way they write their manuals.  And what isn't there is always more important that what is!

Actually, Quark does have an MMU, its just not described in the Datasheet.

The MMU is part of the CPU Core, which is described the Core Hardware Reference Manual and the Core Developer's Manual.   The Quark CPU Core is a complete IA32 implementation,  a little slow but with a few extras for the embedded micro market.  Check out page 20 of the hardware ref, it shows a block diagram of the core.  The three manuals together make up the Quark documentation.  You almost need a monitor for the datasheet, the hardware ref manual printed out and a second monitor for the developers manual to make sense of it all.

This changes everything, so:

1. Quark does after all have an MMU.
2. Having an MMU, it is validly called an applications processor.
3. Having an MMU, it can run full operating systems like Linux with full virtual memory abstraction.
4. Having an MMU, it does not need to run uClinux (which is for MMU-less microcontrollers).

Phew!   And once again, thanks Walt!

I'm very glad to hear that!  Things were looking pretty ugly there for a while ...

And to complete the picture and my (greatly relieved) total reversal, John, there won't be any need for bare-metal programming on the Galileo.  We can happily write bug-ridden code in the cosy abstraction of MMU-protected processes.

Drew Fustini wrote:

 

I will add to my personal defination that SBC must have MMU

You'll be relieved to hear (as I was) that the Quark has one after all, just cloaked in stealth marketing.

The only remaining worry is the harsh and totally non-open licensing on Intel's software downloads.  That however must be a mistake, because they're not allowed to impose such additional restrictions on top of GPL-licensed software.  It'll probably be removed or changed very rapidly once it's pointed out to them.

coder27 wrote:

 

This sounds like it is doing at least some sort of MMU function in translating virtual addresses

to physical addresses.

Yep, it has enough to run a full O/S.  What's more, in the Hardware Reference Manual, Intel explains:

• On-Chip Memory Management Unit — Address management and memory space
   protection mechanisms maintain the integrity of memory in a multi-tasking and
   virtual memory environment. The memory management unit supports both
   segmentation and paging.

and

The memory management unit (MMU) consists of a segmentation unit and a paging
unit which perform address generation. The segmentation unit translates logical
addresses and passes them to the paging and cache units on a 32-bit linear address
bus. Segmentation allows management of the logical address space by providing easy
relocation of data and code and efficient sharing of global resources.

The paging mechanism operates beneath segmentation and is transparent to the
segmentation process. The paging unit translates linear addresses into physical
addresses, which are passed to the cache on a 20-bit bus. Paging is optional and can be
disabled by system software. To implement a virtual memory system, the Intel Quark
Core supports full restartability for all page and segment faults.

Memory is organized into one or more variable length segments, each up to four
Gbytes (232 bytes). A segment can have attributes associated with it that include its
location, size, type (i.e., stack, code, or data), and protection characteristics. Each task
on an Intel Quark Core can have a maximum of 16,381 segments and each are up to
four Gbytes in size. Thus, each task has a maximum of 64 terabytes (trillion bytes) of
virtual memory.

The segmentation unit provides four levels of protection for isolating and protecting
applications and the operating system from each other. The hardware-enforced
protection allows the design of systems with a high degree of software integrity.
The Intel Quark Core has four modes of operation: Real Address Mode (Real Mode),
Protected Mode, Virtual Mode (within Protected Mode), and System Management Mode
(SMM). Real Mode is required primarily to set up the Intel Quark Core for Protected
Mode operation.

Protected Mode provides access to the sophisticated memory management paging and
privilege capabilities of the processor. Within Protected Mode, software can perform a
task switch to enter into tasks designated as Virtual 8086 Mode tasks.

System Management Mode (SMM) provides system designers with a means of adding
new software-controlled features to their computer products that always operate
transparently to the operating system (OS) and software applications. SMM is intended
for use only by system firmware, not by applications software or general purpose
systems software.

In other words, that's a complete MMU, but bizarrely wasn't even hinted at in the Quark datasheet.

We were asking just this week for SBCs with dual NICs for comms applications like firewall/routers.  Well the Galileo has a mini-PCIe slot, so just add a mini PCI-e external NIC like this Syba Mini-PCIe Gigabit Ethernet Card and we have a totally OSHW comms appliance.

nuttcp is ready and waiting.

The Quark datasheet is singularly unhelpful as to the processor's capabilities because only 1 page giving a 10 bullet-point list is devoted to the processor core. The datasheet is far more concerned with the integrated peripheral devices and other matters unique to this SoC. However you can infer that the processor has paging because the list says that Execute-Disable Page Protecton is supported. Also, as it says it's a Pentium and as all Pentiums have protected mode, it's reasonable to infer that it has the same memory management as any other modern x86 processor.

If you read the Developer's Manual or Hardware Reference Manual it becomes crystal clear that the processor core is a full-feature x86 processor containing all the protected mode / paging features you would expect (and which have been in all x86 processors since the 386).

Jeremy Barker wrote:

 

If you read the Developer's Manual or Hardware Reference Manual it becomes crystal clear that the processor core is a full-feature x86 processor containing all the protected mode / paging features you would expect (and which have been in all x86 processors since the 386).

And if you read the whole thread then you'd realize that the Developer's Manual and Hardware Reference Manual didn't come to our attention until Walt Gribben's informative post.

Those two documents aren't linked from Intel's Galileo site under any of its submenus (particularly not in the documents section which lists the Quark SoC Datasheet which would have been the sensible place for them), nor in a very large number of other Intel, Galileo, Arduino and embedded industry sites that describe the board.  This is why Intel's numerous references to microcontroller and to wearables and IoT suggested very strongly that this was a cut-down device with a Pentium inner core but excluding all memory management, and hence was a microcontroller with the x86 instruction set.  That would appeal to many people after all.  The fact that the Quark SoC Datasheet even described a memory region protection feature quite similar to that in Cortex-M3 microcontrollers reinforced that belief.  Not even the Galileo FAQ suggested otherwise --- indeed, it didn't even mention known Linux distros that could be run on the board, which made it possible that uClinux was the only option owing to lack of MMU.  Nothing at all explicitly pointed to an MMU being present.

Armed with your knowledge of the Developer's Manual and Hardware Reference Manual, it's easy to see that this isn't so, but it didn't look that way without that information.  Hindsight is great.

If the SBC becomes significantly more expensive  it has exceeded the value of the Arduino.

Simply you will want more, also the whole benefit of the Arduino was the Comunity and the fact you can get "drivers" for specific wierd interface.

are we going to get those with this new widget ?

Seems to be very much like those cust down 486 style SOCs that you used to see in routers not  unlike the Nat Semi/AMD Geode.

So really that cpu isn't too fantastic one way or another ...Much better than an AVR thing though

Morgane if the only linux this SBC is good for is uC linux maybe we'll have problems getting conventional drivers working for devices such as that GigE PCI-e card.

This SBC market as certainly become a crowded and complicated place.