Have a question about CadSoft EAGLE?  Ask our Expert, Richard! (Archive)

Hi Dusan,

you never bothered me..... I am glad about each message that can help in improving EAGLE.
I did some testing as well and could not find a problem with the Design Rules. So maybe you unintentionally changed the rules or loaded another dru file.

Regards,
Richard

Hi Richard,

I have made more detailed look at it and I think you are right, the rules

seems to be really saved, but if you open the DRC, in the headline the

default rules are declared instead of the really used rules (I think in past

there were the used rules with the indicator of change). I don't know why my

rules were switched do default, perhaps I have unintentionally loaded it,

but the false indication confused me...

I am just finishing one thing I have begun in 6.x and continue only in 5.11

(at least upto the next upgrade), so you will not be bothered from my side

so much now...

Regards  Dusan

Hi Richard,

yes, it is what I would expect, but why if I close project and re-open it,

the Design rules are switched to default? I was surprised by the number of

errors and it is why I noticed this. Now I have to save rules in separate

file and open them after each Eagle restart - perhaps something is wrong at

my side, but I do eherything the same way I am used from past.

Dusan.

Hi Dusan,

the Design Rules are part of the board file. When i look into a version 6 board file I can see the Design Rules section. As you can see here.....

......

......

<designrules>
<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
&lt;p&gt;
The default Design Rules have been set to cover a wide range of applications. Your particular design may have different requirements, so please make the necessary adjustments and save your customized design rules under a new name.</description>
<param name="layerSetup" value="(1*2+3*16)"/>
<param name="mtCopper" value="0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm"/>
<param name="mtIsolate" value="0.38mm 0.71mm 0.38mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm"/>
<param name="mdWireWire" value="8mil"/>
<param name="mdWirePad" value="8mil"/>
<param name="mdWireVia" value="8mil"/>
<param name="mdPadPad" value="8mil"/>
<param name="mdPadVia" value="8mil"/>

......

......

......

All the values are in the file.

Regards,

Richard

Hi Richard,

I am affraid the Design Rules are NOT stored in brd file, at least my 6.1

doesn't store it, which in my opinion is another from long list of bugs with

potentially serious consequences...

Dusan

Hi Richard,

design rules are not more saved with BRD in 6.x? Why?? Do you in CADSoft

think it's better to set it after each time BRD is opened again and again or

be aware not to forget to save it in extra file???

I understand, you must be up to eyes in it, but it is the price for early

release of immature product

Dusan

Hi Joey,

the layer setup is part of the Design Rules, which are stored in the board file. This means hat the board manufacturer can look up the setup if he would load the file in the layout editor and look into the Design Rules.

There he can find the values for thickness and the via lenghts.
But it is always good to tell the board house such details like setup and via lengths in a separate note. So I'ld recommend to tell them all details separately.

Regards,

Richard

Richard,

I recently sent a completed set of gerber files generated from Eagle to a PCB manufacturer. They replied saying that "no stackup information was provided in the gerber files." They needed further information on the thickness/material of the board and each of its layers. I have all of the layer specified in the DRC options for my board. My question is this: Does Eagle automatically generate the "stackup" information or do I need to manually create a text file and include this information for my PCB manufacturer?

Hi Xabi,

you wrote:

But when I see (in the came processor) the different gerber files ,  specially the solder stop mask and the cream frame (layers 29,30,31,32)  there is no difference between a pad and a via.

Layer 29 and 30 contain information about the solder stop mask. Each pad and smd and via will be free of lacquer by default. You can change this and have vias covered as well. (==> Design Rules, Mask tab, Limit).

Layer 31 and 32 contain information about the cream frame or solder paste mask. This on is defined for SMDs only. No pad or vias needs a solder paste.

All these is generated automatically, if you did not set this off and defined your own solder stop mask od cream frame.

Regards,

Richard

Hi Dusan,

there can occur a problem with the ROUTE command and pads/SMDs that are not on grid. You wrote you don't want to have recommended a beta version, but this is exactly what I should do now. The current beta 6.1.1 has this problem fixed. If you don't want to use 6.1.1 you could also try aworkaround in version 6.1.0. When you activate ROUTE and draw a short wire, drop the wire from the mouse (with Escape) and and go on routing again. Don't activate ROUTE again (it is still active), simply click onto the end of the wire and go on. Now the snap problem should be gone.

Regards,
Richard