Hi all,
I was working through some interesting designs on Vitis recently and a colleague of mine brought up a great question.
"What are the actual Vivado implementation settings for the different Vitis --optimize switches?"
Not sure what Vitis is? Check out my other blog series on Vitis to get an idea. If that doesn't help you, you can checkout my webinar I did. That webinar will start building up your skills from the ground up as well as point you to a few really good resources to help get your skills ready to go!
Learning Vitis: 1 Setting up a Virtual Machine
Getting Started with Xilinx Development Tools
For those that just want a 1 sentence summary:
"The Vitis unified software platform enables the development of embedded software and accelerated applications on heterogeneous Xilinx platforms including FPGAs, SoCs, and Versal ACAPs. It provides a unified programming model for accelerating Edge, Cloud, and Hybrid computing applications."
https://www.xilinx.com/products/design-tools/vitis.html
Not sure what Vivado is? You can get a sense from another colleague's blogs on how to use Vivado with the Avnet build scripting:
Avnet HDL git HOWTO (Vivado 2020.1 and earlier)
From Xilinx's website:
"The new Vivado
Design Suite HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure. When coupled with the UltraFast
High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse."
https://www.xilinx.com/products/design-tools/vivado.html
Basically, Vivado is the hardware generation tool for your Xilinx processing elements. The FPGA portion of your design!
Ok, what does all of this really mean? Well, Vitis, with the help of a prebuilt platform, allows someone that is not readily skilled in FPGA design to leverage the power of an FPGA. If you check out my series, you can see that, you extract a prebuilt platform from a download. Point to that as your solution space. Then using a built in example, can go from 0 to solution in less than 5 minutes (not including download and compile time). Even including compile time, in some cases, you could be looking at < 5 minutes!
| Selecting Platform | Selecting Example | Building! |
|---|---|---|
 |  |  |
The key understanding, with all that setup, you really need to understand how to describe your solution in a high level language. Vitis supports "high-level frameworks and languages including Tensorflow and Caffe, C, C++ or Python". Meaning you can test out your code using software modeling, QEMU emulation (now enabled by default in Avnet's Vitis platforms) or any other method of validation you want. Vitis then translates that into the RTL (register-transfer level) language needed for generating the FPGA portion. Well, that is amazing and that is why Vivado gets involved.
| Choosing How far you want to take the build! |
|---|
 |
You see, when you are working with Vitis, similar to just about any compiler (I'm sure there are exceptions), it feels and behaves like a normal software environment. From using the Eclipse based GUI to the "optimization*" flow, Vitis has the ability to try to optimize your design for YOUR specific needs.
That is, at the most simple level, think about compiling C. You can optimize for space, speed, power, or a blend. Some C compilers have so many optimize options, it gets confusing! Personally, when working with C, I just compile with defaults. Someone smarter than I, put a lot of effort into making defaults...well, default for a reason! In my career, if you needed something specifically optimized, you just inlined ASM anyway, so default was always a good choice.
Ok, with all that understanding, what does all this have to do with Vitis and Vivado?
Well, you could go and read UG1393 "Vitis Unified Software Platform Documentation Application Acceleration Development" - and I do recommend that if you have the time. There is a LOT of great information in there. However, that is the issue, there is a LOT of information in there. Over 550 pages! As eluded to above, Vivado gets controlled by Vitis. In Vivado, like in Vitis, you can create designs for efficiency of speed, power, size, etc. All of these buttons/knobs all effect the amount of performance, but also the build time.
For a larger design, you can easily 2x your build time trying to fit a large design into a large part. Of course we are all using UltraFast Design Methodology (see UG949), so we already planned out what we need...right?
Wow, that was a long primer, but trust me, if you need to get into the details, this is worth it. I can recall a handful of times, where you spent months on a solution. Then, the deadline is looming and your only hope is to try to make the thing fit! No time for redos! I can say, we were NOT following UltraFast Design methodology. In fact, I can say, that did not exist back then!
Due to the above mentioned question, Xilinx clarified what maps to what in their two tools. You can see the official response in this answer record:
https://www.xilinx.com/support/answers/75796.html
For example, if you ask Vitis for optimize level 1, Vivado is rerun with Power_DefaultOpt and sdx_optimization_effort_high (which can reduce high fanouts, but takes longer to create a solution)
You can check out your own mappings here:
<Vitis installation folder>/data/vitis/vpp/optMap.xml
As someone that understands more of the hardware side of FPGA design, it is nice to know that when I leverage Vitis (sometimes it is just easier!), I can now understand what the tool is going to try to do under the hood! This helps me to be able to make better decisions with my pragmas (descriptions for how Vitis should interpret the spirit of my C code that it is going to accelerate). This can also help me understand when I am building a design for an UltraZed-EV (a rather large part), why it is taking longer than I expected!
Thanks to the Xilinx team for posting that Answer Record so quickly! I think getting small bits of information out into the hands of our end users is important as it makes their jobs easier!!
*Note I put optimization in quotes as Vitis has many optimization flags, for optimizing the programmable logic portion, software portion, as well as selecting to hardware accelerate functions. For the purpose of this blog, I assume you are already hardware accelerating the correct things and we are more talking about compile flags similar to a C based software design's build flags