I'm a late arriver to the 7 Ways to Leave Your Spartan-6 FPGA program. My device arrived today (June 23). I prepared a first project yesterday. I have prior knowledge with Spartan-6 and ISE, and I know Vivado. I used the Vitis / Vivado toolchain extensively with a Zynq SOC. The exercise yesterday was to see if the initial gap to program for the Spartan-7 is big. And if the Digilent documentation was sufficient to start a simple project. Answer: the gap isn't big, the documentation is sufficient.
I did a simple exercise: make one of the LEDs blink, using one of the on-board clocks, with a clock divider in between. An exercise that I had done in ISE for the Spartan-6, and in Vivado for a Zynq device.
- I used the Digilent documentation to add the board file to an existing Vivado installation,
- retrieved the VHDL clock divider source code that I used before,
- found the pin for the LED 0 in the Digilent constraint file for the Arty S7
- found the clock and reset by creating a project in Vivado and look in the board resources.
Then I created a block design in Vivado, added that clock and the VHDL divider, connected them up and attached the divider output to LED 0.
Here's where I selected clock and reset button. The clock wizard block is placed automatically when you select the system clock.
I could have used the LED resource from the board too, but that's implemented as an AXI device and I want to use simple logic for the first design.
I then created the wrapper, and made it the Top module.
As indicated earlier, I didn't use the Board LED resource, but just made the divider's output pin external and assigned it to LED 0 in the constraints:
Last thing to check: the reset is active low. The clock wizard needs to be adapted for that:
The build completed first time. So far so good. Now, a day later when the board arrived, I'm testing it.
Did it work right first time: yes and no 
: the design did what it was asked to, but the frequency for the LED was too high. It showed as always on, but 50% dimmed.
So I altered the clock to be the lowest possible: 4.7 MHz. And increased the clock divider value from 25000 to 100000. This resulted in a 23 Hz signal at the LED. That's within the range that the eye can detect.
Summary: The switch from ISE to Vivado isn't steep. It took me a few hours (following someone's video) when I started with the Zynq family. And this exercise confirms that. What I did different in Vivado vs ISE is that I used a block design to connect clock, divider and LED. In ISE I did that in the top VHDL source. For the design, the only design difference between the Spartan-6 and 7 in this exercise was the clock source I selected. And that was a deliberate choice. I could just have used PACKAGE_PIN F14 to get a direct 12 MHz clock and link that to the divider.
