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Add Pynq-Z2 board to Vivado

Jan Cumps

Instructions on how to add the Pynq-Z2Pynq-Z2 board to Vivado.

This allows you to create projects and custom FPGA bit streams for it.

 

image source: customer action video after completing the instruction video of Cathal McCabe listed at the end of this post.

 

In the Vivado project creation wizard, there is a possibility to prime your design from a board definition.

You don't need to find out what the exact FPGA is, and what hardware is available.

There are more project preparation tools. Constraint files and TCL files that fully define the board with all possibilities enabled.

This post focuses on the board definition.

 

Get the board file

 

The files listed on pync.io are not available. I found them here.

 

Install and register the board in Vivado

 

Then there are two options.

I used the 2nd option. You have to restart the editor.

 

The result is that you can now create projects that have the right FPGA info for the Pynq-Z2:

 

My goal for this week is to replicate this exercise from Cathal McCabe from the Pynq community:

 

I attached the project to this post, and the jupyter notebook.

I changed some things:

32 bit GPIO instead of 64

A reset input for the Johnson Counter module

Translated the Verilog Counter code to VHDL.

 

 

Pynq - Zync - Vivado series
Add Pynq-Z2 board to Vivado
Learning Xilinx Zynq: port a Spartan 6 PWM example to Pynq
Learning Xilinx Zynq: use AXI with a VHDL example in Pynq
VHDL PWM generator with dead time: the design
Learning Xilinx Zynq: use AXI and MMIO with a VHDL example in Pynq
Learning Xilinx Zynq: port Rotary Decoder from Spartan 6 to Vivado and PYNQ
Learning Xilinx Zynq: FPGA based PWM generator with scroll wheel control
Learning Xilinx Zynq: use RAM design for Altera Cyclone on Vivado and PYNQ
Learning Xilinx Zynq: a Quadrature Oscillator - 2 implementations
Learning Xilinx Zynq: a Quadrature Oscillator - variable frequency
Learning Xilinx Zynq: Hardware Accelerated Software
Automate Repeatable Steps in Vivado
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 1: Vitis HLS
Learning Xilinx Zynq: Try to make my own Accelerated OpenCV Function - 2: Vivado Block Design
Learning Xilinx Zynq: Logic Gates in Vivado
Learning Xilinx Zynq: Interrupt ARM from FPGA fabric
Learning Xilinx Zynq: reuse and combine components to build a multiplexer
PYNQ version 2.7 (Austin) is released
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 1: Turn C++ code into an FPGA IP
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 2: Add the Accelerated IP to a Vivado design
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Part 3: Use the Hardware Accelerated Code in Software
PYNQ and Zynq: the Vitis HLS Accelerator with DMA training - Deep Dive: the data streams between Accelerator IP and ARM processors
Use the ZYNQ XADC with DMA part 1: bare metal
Use the ZYNQ XADC with DMA part 2: get and show samples in PYNQ
VHDL: Convert a Fixed Module into a Generic Module for Reuse
Attachments:
johnson_counter.zip
johnson_counter_jupyter_notebook.zip
Anonymous

  • The Pynq community started a new set of tutorials: https://discuss.pynq.io/t/tutorial-pynq-dma-part-1-hardware-design/3133 .

     

    To get the working set in your jupyter workbooks:

    form /home/xilinx , execute these 3 steps:

    git clone https://github.com/cathalmccabe/PYNQ_tutorials.git
cd jupyter_notebooks
ln -s /home/xilinx/PYNQ_tutorials ./PYNQ_tutorials

     

    If you want to have the Vivado project created automatically (not needed, the bit and .hwh files are provided and instructions to manually create the project are lesson part 1) , there are scripts available.

    If you are on a windows pc, Start Vivado Tcl Shell 2020.1

    cd <directory where you cloned the repository>
cd dma
source dma_tutorial.tcl

     

    The project will be available in a new myproj subfolder.

     

  • I've translated the Johnson Counter from Verilog to VHDL. Another VHDL implementation is available from Jon: VIDOR 4000: Johnson Counter

    We're presenting this project in the PYNQ workshops next week and I can't explain Verilog code . Also a reset signal is added.

     

    library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity jc is
  port ( 
    nLeft_i  : in std_logic;
    nRight_i : in std_logic;
    nStop_i  : in std_logic;
    clk_i    : in std_logic;
    nReset_i : in std_logic;
    q_o      : out std_logic_vector (3 downto 0)
  );
end jc;

architecture Behavioral of jc is

  signal run_s     : std_logic;
  signal dir_s     : std_logic;
  signal outputs_s : std_logic_vector (3 downto 0);

begin

process (clk_i, nReset_i)
begin
  if (rising_edge(clk_i)) then
    if (nReset_i = '0') then
      dir_s <= '0';
      outputs_s <= (others => '0');
    else
      if (nLeft_i = '0') then
        dir_s <= '0';
        run_s <= '1';   
      elsif (nRight_i = '0') then
        dir_s <= '1';
        run_s <= '1';   
      end if;
      if (nStop_i = '0') then
        run_s <= '0';
      end if;
    
      if (run_s = '1') then
        if (dir_s = '1') then -- right
          outputs_s (3 downto 1) <= outputs_s (2 downto 0);
          outputs_s(0) <= not outputs_s(3); 
        else 
          outputs_s (2 downto 0) <= outputs_s (3 downto 1);
          outputs_s(3) <= not outputs_s(0); 
        end if;
      end if;
    end if;
  end if;
end process;

  q_o <= outputs_s;

end Behavioral;

  • The VHDL code used in this series is available as GISTs on github:

    https://gist.github.com/search?l=VHDL&q=user%3Ajancumps

     

    I've put the link to the individual sources in each post.

  • in reply to navadeepganeshu

    After you run synthesis, open the synthesized design.

    then, (I Think under the Windows menu) there is a I/O options item.

    There you can reassign the outputs to different pins. (Your first picture)

    Check the example constraint file for the Z2 to find the PMOD pins.

    Save' and run the steps again to generate the bitfile (and .hwh) file. Including synthesis, I think.

    If you renamed any pins or blocks, regenerate the wrapper for the Block Design.

     

    The TCL file is no longer needed by Pynq. The .hwh plays that role now.

  • , thanks for explaining the full procedure of implementation. The johnson counter did work well.

     

    I was trying to pullout those 4 IOs mapped to onboard LEDs to the PMODA to control stepper motor using the same johnson counter. I believe the synthesis remains same and rerun the implementation directly to change pin mappings over .xdc file.

    I changed pinouts to PMODA's 4 IOs and overwrote the bitstream and .tcl block design file. Then copied to Jupyter notebook and ran the same script(johnson_counter as in video tutorial). I now see still the onboard LEDs blink(scroll over) even if mappings are changed. I am wondering if i missed any critical steps........ Any clues?