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The Art of FPGA Design - Post 37

fpgaguru

Recent Advances in Vivado VHDL-2008 Support

 

Previous posts in this blog were made in the 2018-2019 period. Some of the issues presented were an attempt to work around VHDL-2008 support limitations in Vivado at that point in time. Since then, significant progress has been made in that direction and rather than modifying those old posts I will add a few to this otherwise closed season of my blog to bring the subject up to date.

 

Good VHDL-2008 support is important for designers using an HDL flow, including those who prefer the Verilog or System Verilog HDL language because Vivado lets you freely mix VHDL and Verilog HDL modules in the same design. While the two main HDL languages are more or less equivalent, there are useful language features and design techniques which exist in VHDL but do not have a System Verilog equivalent. As a Verilog designer, you can still take advantage of these nice VHDL language features by using them in lower level VHDL-2008 design hierarchy modules, while still coding the majority of your design in your preferred HDL language.

 

In particular, the unconstrained array ports and especially unconstrained arrays of unconstrained arrays and records, which is a VHDL-2008 feature, do not have System Verilog equivalents and are very useful, especially for DSP type applications. The problem with Vivado at the time when this blog was started was that VHDL-2008 support was relatively limited.

 

VHDL-2008 has a new native type called SFIXED, which is an arbitrary precision fixed point type and you can define generic modules with ports of unconstrained SFIXED type, but more importantly, you can define CFIXED records with real and imaginary fields that are unconstrained SFIXED and then even unconstrained arrays of these two types, SFIXED_VECTOR and CFIXED_VECTOR:

 

  type SFIXED is array(INTEGER range <>) of STD_LOGIC;     – arbitrary precision fixed point signed number, like SIGNED but lower bound can be negative
  type CFIXED is record RE,IM:SFIXED; end record;          – arbitrary precision fixed point complex signed number - not valid in VHDL-93!

  type SFIXED_VECTOR is array(INTEGER range <>) of SFIXED; – unconstrained array of SFIXED - VHDL-2008 only feature
  type CFIXED_VECTOR is array(INTEGER range <>) of CFIXED; – unconstrained array of CFIXED - VHDL-2008 only feature
  type CFIXED_MATRIX is array(INTEGER range <>) of CFIXED_VECTOR; – unconstrained array of CFIXED_VECTOR - VHDL-2008 only feature

 

Unfortunately, these VHDL-2008 features had limited support in previous versions of the Xilinx FPGA design tool Vivado. Support for unconstrained arrays of unconstrained records and arrays exists in Vivado Synthesis since 2018 but not through the predefined VHDL-2008 SFIXED type, you had to use instead an equivalent user defined type with the same name, which is the aproach I used in previous posts of this blog. However, starting with Vivado 2020.2 the VHDL-2008 fixed_generic_pkg generic package which introduces the SFIXED type is finally supported for Synthesis and even more importantly, the same feature will also work in Vivado Simulation starting with Vivado 2021.2, which will be released in October 2021. This means that you will no longer need a third part HDL simulator with good VHDL-2008 support like QuestaSim, you will be finally able to both simulate and implement designs using this feature within Vivado.

 

This is especially good news for students and makers since Vivado has a free edition version and you get a good VHDL-2008 simulator without any size limitations for free, which means you can learn modern HDL design with no initial starting cost.

 

In the next few posts I will show how this new feature works in Vivado 2021.2 and give a few useful design examples.

 

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Parents Comment Children
  • in reply to dubya

    Hi,

     

    The main goal here is to use types for signals and component ports that are unconstrained arrays and build reusable designs that work with any arbitrary range. VHDL-93 has the (range <>) construct to express such things but you cannot have unconstrained arrays of unconstrained arrays and records, which would be very useful for signal processing applications, think vectors of arbitrary size of complex values, with the real and imaginary fields an arbitrary unconstrained array of STD_LOGIC. This feature exists in VHDL-2008 but it took time for the synthesis and especially the simulation tools in Vivado to implement it.

     

    The ELEMENT() function is an attempt to fake this multiple unconstrained feature using VHDL-93 syntax, you would stitch the real and imaginary parts together then the complex elements together in a single VHDL-93 unconstrained array of STD_LOGIC and use these helper functions to access an element of the array. The function needs to know the actual size of the array to be able to slice an element, which is what the N argument is.

     

    Fortunately, these cumbersome workarounds are no longer required. Since 2018.2 I think Vivado synthesis supports well this VHDL-2008 feature, and since 2021.2, which should be released this month, Vivado simulator will do too. I suggest you ignore the old code and try the VHDL-2008 constructs directly in Vivado 2021.2. I plan to add a couple of posts to the old season one blog with code examples on how to do that.

     

    Catalin