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Ultra96-V2 Dual Camera Mezzanine Petalinux Build Instructions

ctammann

As a follow up to the blog I posted on building the hardware design for the out of box image for the ON Semiconductor Dual Camera Mezzanine card, here are the instructions to complete the build with the Petalinux project. The original blog can be found here -
Ultra96-V2 ON Semiconductor Dual Camera Mezzanine hardware build instructions

 

The process of porting the full design over to our Github repo has now been completed. Below I've pasted the instructions to build the full design including Petalinux from the repo. The final command will build the hardware design as part of the script and create the full design.

 

#

# Clone the repositories

#

 

$ cd ~

$ mkdir -p git/avnet

$ cd git/avnet/

$ git clone https://github.com/Avnet/bdf.git

$ git clone https://github.com/Avnet/hdl.git

$ git clone https://github.com/Avnet/petalinux.git

$ cd bdf
$ git checkout master

$ cd ../petalinux

$ git checkout 2020.1

$ cd ../hdl

$ git checkout 2020.1

 

#

# Run the Vivado build script for the Ultra96-V2 dualcam design

#

 

$ cd ../petalinux

$ ./scripts/make_ultra96v2_dualcam.sh

 

 

This process will take a long time and will depend on your pc hardware. When complete, you should see something similar to this:

image

 

Your design has now successfully been built (yay!). So now we need to put it on an SDcard to use on your hardware. Pulling from my colleague Tom Curran's excellent instructions, if you haven't already followed the Getting Started Guide you will need to first partition the SD card with - for example - a 1GB FAT32 boot partition and (assuming you are using the provided 16GB Delkin micro SD card) and a 15GB ext4 partition. I've also attached a handy guide on formatting a new SDcard to this blog.

 

If you have successfully configured your SDcard you are ready to copy over the files. Here are the commands to create the SDcard image. First you must navigate to the folder where the files were generated, then you can copy them over to the proper partitions on your SDcard.

 

$ cd ~/git/avnet/petalinux/projects/ultra96v2_dualcam_2020_1

$ cp ./images/linux/BOOT.BIN /media/training/<UUID of FAT32 partition>/.

$ cp ./images/linux/boot.scr /media/training/<UUID of FAT32 partition>/.

$ cp ./images/linux/image.ub /media/training/<UUID of FAT32 partition>/.

$ sudo rm -rf /media/training/<UUID of ext4 partition>/*

$ sudo tar xvf ./images/linux/rootfs.tar.gz -C /media/training/<UUID of ext4 partition>/

$ sync; sync (VERY IMPORTANT to sync the filesystem BEFORE ejecting the SD card!  If you don't the filesystem may be corrupted. This process can take minutes to complete)

 

You should now be able to run the out of box design from your SDcard with the command

 

$ run_1920_1080

 

The out of box image will show 2 live streams from the cameras on a 1080p monitor.

 

Ultra96-V2Ultra96-V2

Attachments:
imageSD Card Formatting an SD Card.docx
Parents

  • Sorry, I'm on a posting frenzy.

     

    I attempted to run through the steps listed here, however it appears to have stopped and then failed at the "Wait for bitstream to be written" step.

     

    Does this require having gone through the hardware build instructions first?

    Does this require having the Ultra96-V2 connected in JTAG mode before running through this?

     

     

    These are the steps I took to run the PetaLinux build:

     

    vitis20201@vitis20201-VirtualBox:~/develop$ . /tools/Xilinx/Vitis/2020.1/settings64.sh
vitis20201@vitis20201-VirtualBox:~/develop$ . /opt/xilinx/xrt/setup.sh
vitis20201@vitis20201-VirtualBox:~/develop$ . /tools/Xilinx/Vivado/2020.1/settings64.sh


vitis20201@vitis20201-VirtualBox:~/develop$ rm -rf git/

vitis20201@vitis20201-VirtualBox:~/develop$ mkdir -p git/avnet

vitis20201@vitis20201-VirtualBox:~/develop$ cd git/avnet/

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet$ git clone https://github.com/Avnet/bdf.git
Cloning into 'bdf'...
remote: Enumerating objects: 123, done.
remote: Counting objects: 100% (123/123), done.
remote: Compressing objects: 100% (86/86), done.
remote: Total 380 (delta 48), reused 110 (delta 37), pack-reused 257
Receiving objects: 100% (380/380), 23.20 MiB | 4.12 MiB/s, done.
Resolving deltas: 100% (145/145), done.

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet$ git clone https://github.com/Avnet/hdl.git
Cloning into 'hdl'...
remote: Enumerating objects: 669, done.
remote: Counting objects: 100% (669/669), done.
remote: Compressing objects: 100% (244/244), done.
remote: Total 5006 (delta 442), reused 595 (delta 372), pack-reused 4337
Receiving objects: 100% (5006/5006), 14.86 MiB | 2.81 MiB/s, done.
Resolving deltas: 100% (3006/3006), done.
Checking out files: 100% (1874/1874), done.

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet$ git clone https://github.com/Avnet/petalinux.git
Cloning into 'petalinux'...
remote: Enumerating objects: 209, done.
remote: Counting objects: 100% (209/209), done.
remote: Compressing objects: 100% (97/97), done.
remote: Total 3039 (delta 158), reused 150 (delta 106), pack-reused 2830
Receiving objects: 100% (3039/3039), 6.14 MiB | 2.99 MiB/s, done.
Resolving deltas: 100% (1676/1676), done.

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet$ cd bdf/

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/bdf$ git checkout master
Already on 'master'
Your branch is up to date with 'origin/master'.

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/bdf$ cd ../petalinux/

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/petalinux$ git checkout 2020.1
Branch '2020.1' set up to track remote branch '2020.1' from 'origin'.
Switched to a new branch '2020.1'

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/petalinux$ cd ../hdl/

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/hdl$ git checkout 2020.1
Branch '2020.1' set up to track remote branch '2020.1' from 'origin'.
Switched to a new branch '2020.1'
vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/hdl$ ls
avnet_logo.png  Boards  IP  Projects  README.md  Scripts  Software

vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/hdl$ cd ../petalinux/

     

     

    Result of the build:

    // Run Build
vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/petalinux$ ./scripts/make_ultra96v2_dualcam.sh

Verifying repositories ...


Checking Environment (Xilinx tools sourced) ...


Checking 'ultra96v2_dualcam/ULTRA96V2_2020_1' Vivado Project ...


No built Vivado HW project ultra96v2_dualcam/ULTRA96V2_2020_1 found.
Will build the hardware platform now.


****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source make_ultra96v2_dualcam.tcl -notrace

*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-                                                     -*
*-        Welcome to the Avnet Project Builder         -*
*-                                                     -*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*

BDF path set to /home/vitis20201/develop/git/avnet/bdf 



+------------------+------------------------------------+
| Setting          |     Configuration                  |
+------------------+------------------------------------+
| Board            |     ULTRA96V2                      |
+------------------+------------------------------------+
| Project          |     ultra96v2_dualcam              |
+------------------+------------------------------------+
| SDK              |     no                             |
+------------------+------------------------------------+
| No Close Project |     no                             |
+------------------+------------------------------------+
| Version override |     yes                            |
+------------------+------------------------------------+
| Device           |     zynqmp                         |
+------------------+------------------------------------+



Overriding Version Check, Please Check the Design for Validity!


*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*
 Selected Board and Project as:
 ULTRA96V2 and ultra96v2_dualcam
*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*


Not Requesting Tag
Setting Up Project ultra96v2_dualcam...

***** Creating Vivado Project...
create_project: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 2032.109 ; gain = 2.016 ; free physical = 4557 ; free virtual = 8669
***** Assigning Vivado Project board_part Property to ultra96v2...

***** Generating IP...

***** Updating Vivado to include IP Folder
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/vitis20201/develop/git/avnet/hdl/IP'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.1/data/ip'.
update_ip_catalog: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 2032.109 ; gain = 0.000 ; free physical = 4506 ; free virtual = 8655

***** Creating Block Design...
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
create_bd_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2096.023 ; gain = 21.051 ; free physical = 4449 ; free virtual = 8637

***** Add defined IP blocks to Block Design...
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-i
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'RX_EQUALIZATION_S' from 'NONE' to 'EQ_NONE' has been ignored for IP 'ULTRA96V2_mipi_csi2_rx_subsyst_0_0/bd_1b41/bd_1b41_phy_0/bd_1b41_phy_0_hssio_rx'
create_bd_cell: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2594.449 ; gain = 0.000 ; free physical = 3195 ; free virtual = 7787
create_bd_cell: Time (s): cpu = 00:00:38 ; elapsed = 00:01:21 . Memory (MB): peak = 2594.449 ; gain = 498.422 ; free physical = 3192 ; free virtual = 7784
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'RX_EQUALIZATION_S' from 'NONE' to 'EQ_NONE' has been ignored for IP 'ULTRA96V2_mipi_csi2_rx_subsyst_0_0/bd_1b41/bd_1b41_phy_0/bd_1b41_phy_0_hssio_rx'
create_bd_cell: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2594.449 ; gain = 0.000 ; free physical = 3172 ; free virtual = 7765
WARNING: [BD 41-1731] Type mismatch between connected pins: /system_rst_out(rst) and /phy/system_rst_out(undef)
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axi_mm/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axi_mm/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /smartconnect_1/aresetn(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /vdma_trunc/aresetn(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /vdma_pad/aresetn(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /video_router/M03_AXIS_ARESETN(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /video_router/S03_AXIS_ARESETN(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /video_router/S09_AXIS_ARESETN(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /dint/ap_rst_n(rst)
WARNING: [BD 41-1731] Type mismatch between connected pins: /reset_sel_axi_mm/gpio_io_o(undef) and /deint_cc/m_axis_aresetn(rst)
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axis/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axis/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /deint_ss/m_axis_tuser is being overridden by the user. This pin will not be connected as a part of interface connection M_AXIS
WARNING: [BD 41-1306] The connection to interface pin /deint_cc/s_axis_tuser is being overridden by the user. This pin will not be connected as a part of interface connection S_AXIS
WARNING: [BD 41-1306] The connection to interface pin /deint_cc/m_axis_tuser is being overridden by the user. This pin will not be connected as a part of interface connection M_AXIS
WARNING: [BD 41-1306] The connection to interface pin /dint/s_axis_video_TUSER is being overridden by the user. This pin will not be connected as a part of interface connection s_axis_video
1
true
true
Slave segment '/axi_vdma/S_AXI_LITE/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/csc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/dint/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
Slave segment '/hcr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0003_0000 [ 64K ]>.
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0004_0000 [ 64K ]>.
Slave segment '/ltr/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0005_0000 [ 64K ]>.
Slave segment '/reset_sel_axi_mm/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0006_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0007_0000 [ 64K ]>.
Slave segment '/vcr_i/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0008_0000 [ 64K ]>.
Slave segment '/vcr_o/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0009_0000 [ 64K ]>.
Slave segment '/video_router/xbar/S_AXI_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000A_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x000B_0000 [ 64K ]>.
create_bd_cell: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2594.449 ; gain = 0.000 ; free physical = 3097 ; free virtual = 7694
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axis/gpio_io_i is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1306] The connection to interface pin /reset_sel_axis/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
0
false
false
Slave segment '/hsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0000_0000 [ 64K ]>.
Slave segment '/reset_sel_axis/S_AXI/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0001_0000 [ 64K ]>.
Slave segment '/vsc/s_axi_CTRL/Reg' is being assigned into address space '/s_axi_ctrl' at <0x0002_0000 [ 64K ]>.
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ui/bd_8b17350d.ui> 
WARNING: [BD 41-1306] The connection to interface pin /GPIO/axi_gpio_0/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-1306] The connection to interface pin /LIVE_VIDEO_DP/alpha_control_0/video_active_out is being overridden by the user. This pin will not be connected as a part of interface connection video_out
WARNING: [BD 41-1306] The connection to interface pin /LIVE_VIDEO_DP/alpha_control_0/video_dout is being overridden by the user. This pin will not be connected as a part of interface connection video_out
WARNING: [BD 41-1306] The connection to interface pin /LIVE_VIDEO_DP/alpha_control_0/video_hsync_out is being overridden by the user. This pin will not be connected as a part of interface connection video_out
WARNING: [BD 41-1306] The connection to interface pin /LIVE_VIDEO_DP/alpha_control_0/video_vsync_out is being overridden by the user. This pin will not be connected as a part of interface connection video_out
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
CRITICAL WARNING: [PSU-1]  Actual device frequency is : 479.995209. Minimum actual device frequency supported for DDR for current part is 500.000000. 
create_bd_cell: Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2717.453 ; gain = 106.996 ; free physical = 2937 ; free virtual = 7568
INFO: [PSU-0] Address Range of DDR (0x1ff00000 to 0x1fffffff) is reserved by PMU for internal purpose.
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
create_bd_cell: Time (s): cpu = 00:00:47 ; elapsed = 00:01:32 . Memory (MB): peak = 3177.770 ; gain = 460.316 ; free physical = 2451 ; free virtual = 7102
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_DIVCLK_DIVIDE' from '1' to '5' has been ignored for IP 'clk_wiz'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKFBOUT_MULT_F' from '12.000' to '32.000' has been ignored for IP 'clk_wiz'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN1_PERIOD' from '10.000' to '5.333' has been ignored for IP 'clk_wiz'
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'MMCM_CLKIN2_PERIOD' from '10.000' to '10.0' has been ignored for IP 'clk_wiz'
Slave segment '/ZYNQ/zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/CAPTURE_PIPLINE/v_frmbuf_wr_0/Data_m_axi_mm_video' at <0x0000_0000 [ 2G ]>.
Slave segment '/ZYNQ/zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW' is being assigned into address space '/LIVE_VIDEO_DP/v_frmbuf_rd_0/Data_m_axi_mm_video' at <0x0000_0000 [ 2G ]>.
Slave segment '/LIVE_VIDEO_DP/alpha_control_0/S00_AXI/S00_AXI_reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA001_1000 [ 4K ]>.
Slave segment '/GPIO/axi_gpio_0/S_AXI/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA004_0000 [ 4K ]>.
Slave segment '/CAPTURE_PIPLINE/mipi_csi2_rx_subsyst_0/csirxss_s_axi/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA002_0000 [ 128K ]>.
Slave segment '/LIVE_VIDEO_DP/v_frmbuf_rd_0/s_axi_CTRL/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA00C_0000 [ 64K ]>.
Slave segment '/CAPTURE_PIPLINE/v_frmbuf_wr_0/s_axi_CTRL/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA000_0000 [ 64K ]>.
Slave segment '/LIVE_VIDEO_DP/v_osd_0/ctrl/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA007_0000 [ 64K ]>.
Slave segment '/CAPTURE_PIPLINE/v_proc_ss_0/s_axi_ctrl/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA008_0000 [ 256K ]>.
Slave segment '/LIVE_VIDEO_DP/v_tc_0/ctrl/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA006_0000 [ 64K ]>.
Slave segment '/LIVE_VIDEO_DP/v_tpg_0/s_axi_CTRL/Reg' is being assigned into address space '/ZYNQ/zynq_ultra_ps_e_0/Data' at <0xA005_0000 [ 64K ]>.

***** General Configuration for Design...

***** Adding Source Files to Block Design...
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m00_exit_pipeline/m00_exit' is ignored
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m01_exit_pipeline/m01_exit' is ignored
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m02_exit_pipeline/m02_exit' is ignored
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change 
INFO: [xilinx.com:ip:v_axi4s_vid_out:4.0-913] /LIVE_VIDEO_DP/v_axi4s_vid_out_0 C_S_AXIS_VIDEO_FORMAT has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:v_axi4s_vid_out:4.0-913] /LIVE_VIDEO_DP/v_axi4s_vid_out_0 C_S_AXIS_VIDEO_FORMAT has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz clk_wiz propagate
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ZYNQ/zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /ZYNQ/axi_mem_intercon/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ZYNQ/zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /ZYNQ/axi_mem_intercon/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_cc/M_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_cc/M_AXI(16)
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_rid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_bid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_awid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_arid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_arid'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/synth/ULTRA96V2.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_rid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_bid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_awid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_arid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_arid'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/sim/ULTRA96V2.v
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/hdl/ULTRA96V2_wrapper.v
make_wrapper: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 3261.922 ; gain = 84.152 ; free physical = 2343 ; free virtual = 7008

***** Adding Vitis Directves to Design...
update_compile_order: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 3269.949 ; gain = 8.027 ; free physical = 2335 ; free virtual = 7009
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sources_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'

***** Building Binary...
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m00_exit_pipeline/m00_exit' is ignored
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m01_exit_pipeline/m01_exit' is ignored
WARNING: [BD 41-721] Attempt to set value '0' on disabled parameter 'HAS_LOCK' of cell '/m02_exit_pipeline/m02_exit' is ignored
INFO: [xilinx.com:ip:v_axi4s_vid_out:4.0-913] /LIVE_VIDEO_DP/v_axi4s_vid_out_0 C_S_AXIS_VIDEO_FORMAT has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:v_axi4s_vid_out:4.0-913] /LIVE_VIDEO_DP/v_axi4s_vid_out_0 C_S_AXIS_VIDEO_FORMAT has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz clk_wiz propagate
INFO: [xilinx.com:ip:clk_wiz:6.0-1] /clk_wiz clk_wiz propagate
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ZYNQ/zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /ZYNQ/axi_mem_intercon/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ZYNQ/zynq_ultra_ps_e_0/S_AXI_HP0_FPD(1) and /ZYNQ/axi_mem_intercon/xbar/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_cc/M_AXI(16)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_ds/S_AXI(0) and /ZYNQ/ps8_0_axi_periph/s00_couplers/auto_cc/M_AXI(16)
Wrote  : </home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ULTRA96V2.bd> 
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_rid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_bid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_awid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_arid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_arid'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/synth/ULTRA96V2.v
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_rid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_rid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/xbar/m_axi_bid'(2) to pin: '/ZYNQ/axi_mem_intercon/m00_couplers/S_AXI_bid'(6) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s00_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S00_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_arlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_arlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/axi_mem_intercon/s03_mmu/s_axi_awlock'(1) to pin: '/ZYNQ/axi_mem_intercon/S03_AXI_awlock'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_awid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_awid'(2) - Only lower order bits will be connected.
WARNING: [BD 41-2384] Width mismatch when connecting pin: '/ZYNQ/zynq_ultra_ps_e_0/saxigp2_arid'(6) to pin: '/ZYNQ/axi_mem_intercon/M00_AXI_arid'(2) - Only lower order bits will be connected.
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/sim/ULTRA96V2.v
VHDL Output written to : /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/hdl/ULTRA96V2_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/axis_subset_converter_1 .
Exporting to file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_mipi_csi2_rx_subsyst_0_0/bd_0/hw_handoff/ULTRA96V2_mipi_csi2_rx_subsyst_0_0.hwh
Generated Block Design Tcl file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_mipi_csi2_rx_subsyst_0_0/bd_0/hw_handoff/ULTRA96V2_mipi_csi2_rx_subsyst_0_0_bd.tcl
Generated Hardware Definition File /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_mipi_csi2_rx_subsyst_0_0/bd_0/synth/ULTRA96V2_mipi_csi2_rx_subsyst_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/mipi_csi2_rx_subsyst_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/proc_sys_reset_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/proc_sys_reset_2 .
WARNING: [IP_Flow 19-1971] File named "sim/ULTRA96V2_v_frmbuf_wr_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/v_frmbuf_wr_0 .
Exporting to file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_1/hw_handoff/bd_793d_smartconnect_0_0.hwh
Generated Block Design Tcl file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_1/hw_handoff/bd_793d_smartconnect_0_0_bd.tcl
Generated Hardware Definition File /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_1/synth/bd_793d_smartconnect_0_0.hwdef
WARNING: [IP_Flow 19-1971] File named "sim/bd_793d_vsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
WARNING: [IP_Flow 19-1971] File named "sim/bd_793d_hsc_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
Exporting to file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_0/hw_handoff/ULTRA96V2_v_proc_ss_0_0.hwh
Generated Block Design Tcl file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_0/hw_handoff/ULTRA96V2_v_proc_ss_0_0_bd.tcl
Generated Hardware Definition File /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_v_proc_ss_0_0/bd_0/synth/ULTRA96V2_v_proc_ss_0_0.hwdef
INFO: [BD 41-1029] Generation completed for the IP Integrator block CAPTURE_PIPLINE/v_proc_ss_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/axi_gpio_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_4 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block GPIO/xlslice_5 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/Subset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/alpha_control_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/axis_subset_converter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/axis_subset_converter_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/proc_sys_reset_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/proc_sys_reset_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/v_axi4s_vid_out_0 .
WARNING: [IP_Flow 19-1971] File named "sim/ULTRA96V2_v_frmbuf_rd_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/v_frmbuf_rd_0 .
WARNING: [IP_Flow 19-650] IP license key 'v_osd@2013.03' is enabled with a Design_Linking license.
WARNING: [IP_Flow 19-650] IP license key 'v_osd@2013.03' is enabled with a Design_Linking license.
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/v_osd_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/v_tc_0 .
WARNING: [IP_Flow 19-1971] File named "sim/ULTRA96V2_v_tpg_0_0.v" already exists in file group "xilinx_verilogsimulationwrapper", cannot add it again.
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/v_tpg_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/xlconstant_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block LIVE_VIDEO_DP/xlconstant_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/axi_mem_intercon/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/ps8_0_axi_periph/xbar .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/rst_clk_wiz_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/rst_ps8_0_100M .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/xlconcat_0 .
INFO: [xilinx.com:ip:zynq_ultra_ps_e:3.3-0] ULTRA96V2_zynq_ultra_ps_e_0_0: 
Changes in your design (including the PCW configuration settings) are not automatically exported from Vivado to Xilinx's SDK, Petalinux or Yocto.
This is by design to avoid disrupting existing embedded development efforts. To have any changes of your design taking effect in the embedded software flow please export your
design by going through Vivado's main menu, click on File, then Export finally select Export Hardware, please ensure you click on the Include BitStream option.
The auto-generated HDF file is all you need to import in Xilinx's SDK, Petalinux or Yocto for your changes to be reflected in the Embedded Software Flow.
For more information, please consult PG201, section: Exporting PCW Settings to Embedded Software Flows
INFO: [PSU-0] Address Range of DDR (0x7ff00000 to 0x7fffffff) is reserved by PMU for internal purpose.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI_HPM0_FPD'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI_HP0_FPD'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/zynq_ultra_ps_e_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_auto_us_0/ULTRA96V2_auto_us_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/axi_mem_intercon/s03_couplers/auto_us .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/axi_mem_intercon/s00_mmu .
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/axi_mem_intercon/s03_mmu .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_auto_cc_0/ULTRA96V2_auto_cc_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/ps8_0_axi_periph/s00_couplers/auto_cc .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_auto_ds_0/ULTRA96V2_auto_ds_0_ooc.xdc'
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'S_AXI'. A default connection has been created.
WARNING: [IP_Flow 19-5611] Unable to find an associated reset port for the interface 'M_AXI'. A default connection has been created.
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/ps8_0_axi_periph/s00_couplers/auto_ds .
WARNING: [IP_Flow 19-4994] Overwriting existing constraint file '/home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/ip/ULTRA96V2_auto_pc_0/ULTRA96V2_auto_pc_0_ooc.xdc'
INFO: [BD 41-1029] Generation completed for the IP Integrator block ZYNQ/ps8_0_axi_periph/s00_couplers/auto_pc .
Exporting to file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/hw_handoff/ULTRA96V2.hwh
Generated Block Design Tcl file /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/hw_handoff/ULTRA96V2_bd.tcl
Generated Hardware Definition File /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.srcs/sources_1/bd/ULTRA96V2/synth/ULTRA96V2.hwdef
[Wed Mar 17 00:12:00 2021] Launched bd_793d_hsc_0_synth_1, ULTRA96V2_mipi_csi2_rx_subsyst_0_0_synth_1, bd_793d_rst_axis_0_synth_1, ULTRA96V2_axis_subset_converter_1_0_synth_1, bd_793d_input_size_set_0_synth_1, bd_793d_reset_sel_axis_0_synth_1, ULTRA96V2_proc_sys_reset_2_0_synth_1, ULTRA96V2_v_proc_ss_0_0_synth_1, ULTRA96V2_v_frmbuf_wr_0_0_synth_1, bd_793d_smartconnect_0_0_synth_1, bd_1b41_rx_0_synth_1, bd_1b41_r_sync_0_synth_1, bd_793d_axis_register_slice_0_0_synth_1, bd_793d_vsc_0_synth_1, bd_1b41_xbar_0_synth_1, bd_1b41_phy_0_synth_1, bd_793d_axis_fifo_0_synth_1, ULTRA96V2_proc_sys_reset_1_0_synth_1, bd_1b41_vfb_0_0_synth_1, ULTRA96V2_axi_gpio_0_0_synth_1, ULTRA96V2_Subset_0_0_synth_1, ULTRA96V2_alpha_control_0_0_synth_1, ULTRA96V2_axis_subset_converter_0_0_synth_1, ULTRA96V2_axis_subset_converter_2_0_synth_1, ULTRA96V2_proc_sys_reset_0_0_synth_1, ULTRA96V2_proc_sys_reset_2_1_synth_1, ULTRA96V2_v_axi4s_vid_out_0_0_synth_1, ULTRA96V2_v_frmbuf_rd_0_0_synth_1, ULTRA96V2_v_osd_0_0_synth_1, ULTRA96V2_v_tc_0_0_synth_1, ULTRA96V2_v_tpg_0_0_synth_1, ULTRA96V2_clk_wiz_0_synth_1, ULTRA96V2_auto_us_0_synth_1, ULTRA96V2_s00_mmu_0_synth_1, ULTRA96V2_s03_mmu_0_synth_1, ULTRA96V2_auto_cc_0_synth_1, ULTRA96V2_auto_ds_0_synth_1, ULTRA96V2_auto_pc_0_synth_1, ULTRA96V2_xbar_0_synth_1, ULTRA96V2_xbar_1_synth_1, ULTRA96V2_rst_clk_wiz_100M_0_synth_1, ULTRA96V2_rst_ps8_0_100M_0_synth_1, ULTRA96V2_zynq_ultra_ps_e_0_0_synth_1, synth_1...
Run output will be captured here:
bd_793d_hsc_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_hsc_0_synth_1/runme.log
ULTRA96V2_mipi_csi2_rx_subsyst_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_mipi_csi2_rx_subsyst_0_0_synth_1/runme.log
bd_793d_rst_axis_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_rst_axis_0_synth_1/runme.log
ULTRA96V2_axis_subset_converter_1_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_axis_subset_converter_1_0_synth_1/runme.log
bd_793d_input_size_set_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_input_size_set_0_synth_1/runme.log
bd_793d_reset_sel_axis_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_reset_sel_axis_0_synth_1/runme.log
ULTRA96V2_proc_sys_reset_2_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_proc_sys_reset_2_0_synth_1/runme.log
ULTRA96V2_v_proc_ss_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_proc_ss_0_0_synth_1/runme.log
ULTRA96V2_v_frmbuf_wr_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_frmbuf_wr_0_0_synth_1/runme.log
bd_793d_smartconnect_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_smartconnect_0_0_synth_1/runme.log
bd_1b41_rx_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_1b41_rx_0_synth_1/runme.log
bd_1b41_r_sync_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_1b41_r_sync_0_synth_1/runme.log
bd_793d_axis_register_slice_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_axis_register_slice_0_0_synth_1/runme.log
bd_793d_vsc_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_vsc_0_synth_1/runme.log
bd_1b41_xbar_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_1b41_xbar_0_synth_1/runme.log
bd_1b41_phy_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_1b41_phy_0_synth_1/runme.log
bd_793d_axis_fifo_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_793d_axis_fifo_0_synth_1/runme.log
ULTRA96V2_proc_sys_reset_1_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_proc_sys_reset_1_0_synth_1/runme.log
bd_1b41_vfb_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/bd_1b41_vfb_0_0_synth_1/runme.log
ULTRA96V2_axi_gpio_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_axi_gpio_0_0_synth_1/runme.log
ULTRA96V2_Subset_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_Subset_0_0_synth_1/runme.log
ULTRA96V2_alpha_control_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_alpha_control_0_0_synth_1/runme.log
ULTRA96V2_axis_subset_converter_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_axis_subset_converter_0_0_synth_1/runme.log
ULTRA96V2_axis_subset_converter_2_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_axis_subset_converter_2_0_synth_1/runme.log
ULTRA96V2_proc_sys_reset_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_proc_sys_reset_0_0_synth_1/runme.log
ULTRA96V2_proc_sys_reset_2_1_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_proc_sys_reset_2_1_synth_1/runme.log
ULTRA96V2_v_axi4s_vid_out_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_axi4s_vid_out_0_0_synth_1/runme.log
ULTRA96V2_v_frmbuf_rd_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_frmbuf_rd_0_0_synth_1/runme.log
ULTRA96V2_v_osd_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_osd_0_0_synth_1/runme.log
ULTRA96V2_v_tc_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_tc_0_0_synth_1/runme.log
ULTRA96V2_v_tpg_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_v_tpg_0_0_synth_1/runme.log
ULTRA96V2_clk_wiz_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_clk_wiz_0_synth_1/runme.log
ULTRA96V2_auto_us_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_auto_us_0_synth_1/runme.log
ULTRA96V2_s00_mmu_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_s00_mmu_0_synth_1/runme.log
ULTRA96V2_s03_mmu_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_s03_mmu_0_synth_1/runme.log
ULTRA96V2_auto_cc_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_auto_cc_0_synth_1/runme.log
ULTRA96V2_auto_ds_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_auto_ds_0_synth_1/runme.log
ULTRA96V2_auto_pc_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_auto_pc_0_synth_1/runme.log
ULTRA96V2_xbar_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_xbar_0_synth_1/runme.log
ULTRA96V2_xbar_1_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_xbar_1_synth_1/runme.log
ULTRA96V2_rst_clk_wiz_100M_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_rst_clk_wiz_100M_0_synth_1/runme.log
ULTRA96V2_rst_ps8_0_100M_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_rst_ps8_0_100M_0_synth_1/runme.log
ULTRA96V2_zynq_ultra_ps_e_0_0_synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/ULTRA96V2_zynq_ultra_ps_e_0_0_synth_1/runme.log
synth_1: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/synth_1/runme.log
[Wed Mar 17 00:12:01 2021] Launched impl_1...
Run output will be captured here: /home/vitis20201/develop/git/avnet/hdl/Projects/ultra96v2_dualcam/ULTRA96V2_2020_1/ULTRA96V2.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:41 ; elapsed = 00:01:55 . Memory (MB): peak = 3842.887 ; gain = 572.938 ; free physical = 2188 ; free virtual = 6962

***** ...
[Wed Mar 17 00:12:01 2021] Waiting for impl_1 to finish...
/tools/Xilinx/Vivado/2020.1/bin/loader: line 286:  2934 Killed                  "$RDI_PROG" "$@"
vitis20201@vitis20201-VirtualBox:~/develop/git/avnet/petalinux$

  • in reply to jomoenginer

    The VM changes, along with adding the Voucher License, seem to have eliminated the issues I was having with the build. It did take about a day and half to compile though.

     

    After copying the image to a SD card and then booting the Ultra96-V2 with Dual Cam Mezz, I see this in the JTAG/UART term window:

    Starting random number generator daemon
Initializing available sources

Failed to init entropy source hwrng

[   20.839061] add_virtual_intf name[mon.p2p0] vnum[2], nl-type[6]
[   20.845564] add_virtual_intf:monitor name[p2p0] vnum[2], idx[1], wilc-type[1], nl-type[3]
[   20.907533] start_ap,dev[p2p0]
[   23.264212] random: crng init done
[   23.649047] ap1302 4-003c: CRC mismatch: expected 0xf80f, got 0x1cae
[   23.671867] ap1302 4-003c: AP1302 revision 0.2.6 detected
Initializing AES buffer

Enabling JITTER rng support

Initializing entropy source jitter

     

    The CRC mismatch for the ap1302 image sensor device concerns me.

  • in reply to jomoenginer

    Hi ,

     

    Yes, I agree that seeing the CRC mismatch is unsettling, but I asked our driver developer about this and the explanation that I got is that it is mostly innocuous.

     

    The driver will attempt to load the AP1302 configuration/firmware blob 3 times before giving up and assuming that an AP1302 is not attached to the I2C bus as expected.  What you see with the CRC mismatch message is that at least one of those 3 attempts to configure the AP1302 failed the CRC check step at the end.  However, when you see the "AP1302 revision 0.2.6 detected" message that indicates that a subsequent AP1302 configuration attempt did succeed and pass the CRC check and the driver considers the AP1302 properly probed and configured.  If it also happens that the AP1302 blob transfer fails 3 times in a row, then the driver considers failure to probe the AP1302 device. If that were to happen, I would recommend rebooting the Ultra96, but this scenario is very unlikely as we have only experienced it once or twice.

     

    I know it sounds bad to hear that explanation at first, but when you are considering that we transfer a relatively large amount of data (the AP1302 blob) over the serial I2C interface and there is a good chance that a single bit can get corrupted and trigger the CRC mismatch error, then perhaps it is not so alarming in the grand scheme of things.  I don't think you will see the CRC mismatch message all of the time and I think you can safely ignore it when you do.  If it becomes an issue, one possible work around could be to lower the Zynq UltraScale+ I2C clock frequency to decrease the bit error rate when transferring the AP1302 blob, but then that has the tradeoff of extending out the AP1302 configuration time during the driver initialization as well.

     

    Best Regards,

     

    -Kevin

Comment
  • in reply to jomoenginer

    Hi ,

     

    Yes, I agree that seeing the CRC mismatch is unsettling, but I asked our driver developer about this and the explanation that I got is that it is mostly innocuous.

     

    The driver will attempt to load the AP1302 configuration/firmware blob 3 times before giving up and assuming that an AP1302 is not attached to the I2C bus as expected.  What you see with the CRC mismatch message is that at least one of those 3 attempts to configure the AP1302 failed the CRC check step at the end.  However, when you see the "AP1302 revision 0.2.6 detected" message that indicates that a subsequent AP1302 configuration attempt did succeed and pass the CRC check and the driver considers the AP1302 properly probed and configured.  If it also happens that the AP1302 blob transfer fails 3 times in a row, then the driver considers failure to probe the AP1302 device. If that were to happen, I would recommend rebooting the Ultra96, but this scenario is very unlikely as we have only experienced it once or twice.

     

    I know it sounds bad to hear that explanation at first, but when you are considering that we transfer a relatively large amount of data (the AP1302 blob) over the serial I2C interface and there is a good chance that a single bit can get corrupted and trigger the CRC mismatch error, then perhaps it is not so alarming in the grand scheme of things.  I don't think you will see the CRC mismatch message all of the time and I think you can safely ignore it when you do.  If it becomes an issue, one possible work around could be to lower the Zynq UltraScale+ I2C clock frequency to decrease the bit error rate when transferring the AP1302 blob, but then that has the tradeoff of extending out the AP1302 configuration time during the driver initialization as well.

     

    Best Regards,

     

    -Kevin

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